Datasheet

PCR
ROM
Interface
ESM
ROM
Clock Controller
FSM
and
Sequence
Controller
COMP
BLK
segment_Reset
misr_out
Global Clock
Controller
STC
STC REG
BLOCK
STC_BYPASS/
ATE Interface
VBUSP
Inteface
Test
Controller
SEG1
Bisted SCU
including
DBIST
m
SEG0
Bisted CPU1
and CPU2
DBIST
including
www.ti.com General Description
10.1.3.3 Peripheral Bus (VBUSP) Interface
STC control registers are accessed through Peripheral Bus (VBUSP) Interface. During application
programming, configuration registers are programmed through the Peripheral Bus Interface to enable and
run the self-test controller.
Figure 10-1. Block Diagram for STC With Multiple Segments
423
SPNU563–May 2014 Self-Test Controller (STC) Module
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