Datasheet

Data Waitstates
RAM
RWAIT Setting
Flash (Main Memory)
HCLK = 0MHz
HCLK = 0MHz
90MHz45MHz
0 1 3
0
135MHz
2
EWAIT Setting
HCLK = 0MHz
1 64
150MHz
150MHz
150MHz
EEPROM Flash (BUS2)
7
60MHz 90MHz 120MHz
45MHz
2
75MHz
3
8
135MHz105MHz
5
58
TMS570LC4357
SPNS195C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Figure 5-1. Wait States Scheme
L2 flash is clocked by HCLK and is limited to maximum 150 MHz. The L2 flash can support zero data wait
state up to 45 MHz.