Datasheet

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Table 2-1. Definition of Terms (continued)
Acronym/Term Full Form Description
IOMM IO Multiplexing Module This module controls the multiplexing on the device I/Os. Multiple functions can
be multiplexed onto the same device IO. Through IOMM module, user can
enable a specific function onto a device pin.
PMM Power Management Module This module controls the clock gating to the various logic power domains in the
device. Through PMM, user can place a power domain among Active, Idle or
Off modes. This device does not implement physical power domains in which
power can be turned off. Trying to turn off a power domain has no effect on this
device in terms of power consumption but clocks will be gated off to remove
dynamic power. Idle and Off modes in this device behave the same from power
consumption perspective.
EPC Error Profiling Controller This module is used to profile the occurrences of single bit and double bit ECC
errors detected by the CPU and the CPU Interconnect Subsystem.
SCM SCR Control Module This module is used to change certain configurations such as timeout counters
of the CPU Interconnect Subsystem. This module is also used to initiate selftest
for the CPU Interconnect Subsystem.
SYS System Module This module contains the housekeeping logic to control and log overall system
functions and status such as setting up the clock sources, clock domains,
generation and reception of reset sources.
CCM-R5F CPU Compare Module for During lockstep mode, the outputs of the two CPUs are compared on each
Cortex-R5F core CPU clock cycle by this module. Any miscompare is flagged as an error of the
highest severity level. The outputs of the two VIMs in lockstep are also
compared on each cycle by this module.
STCx Selftest Controller There are two STC modules in this device. One is used to test the CPU
subsystem including both CPU cores and/or the ACP component using the
Deterministic Logic Bist Controller as the test engine. The other STC is used to
test either or both the N2HETs in the device.
DCCx Dual Clock Comparator This module is primarily intended for use to determine the accuracy of a clock
signal during the execution of an application. An additional use of this module is
to measure the frequency of a selectable clock source, using the input clock as
a reference.
RTI Real Time Interrupt module RTI module provides timer functionality for operating systems and for
benchmarking code. The module incorporates several counters, which define
the timebases needed for scheduling in the operating system.
VIM Vectored Interrupt Manager VIM provides hardware assistance for prioritizing and controlling the many
interrupt sources present on a device. There are two VIMs in this device. When
the device is configured in lockstep mode, the two VIMs are also in lockstep.
The outputs of the two VIMs are compared cycle by cycle by the CCM-R5
module.
ESM Error Signal Module ESM collects and reports the various error conditions on the device. The error
condition is categorized based on a severity level. Error response is then
generated based on the category of the error. Possible error responses include
a low priority interrupt, high priority NMI interrupt and an external pin action.
2.1.3 Bus Master / Slave Access Privileges
This device implements some restrictions on the bus slave access privileges in order to improve the
overall throughput of the interconnect shown in Figure 2-1. Table 4-1 shows the implemented point to
point connections between the masters and slaves connected to the Peripheral Interconnect Subsystem.
Table 4-3 lists the implemented point to point connections between the masters and slaves connected to
the CPU Interconnect Subsystem.
2.1.4 CPU Interconnect Subsystem SDC MMR Port
The CPU Interconnect Subsystem SDC MMR Port is a special slave to the Peripheral Interconnect
Subsystem. It is memory mapped at starting address of FA00 0000h. Various status registers pertaining to
the diagnostics of the CPU Interconnect Subsystem can be access through this slave port. The CPU
Interconnect Subsystem contains built-in hardware diagnostic checkers which will constantly watch
transactions flowing through the interconnect. There is a checker for each master and slave attached to
the CPU Interconnect Subsystem. The checker checks the expected behavior against the generated
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SPNU563–May 2014 Architecture
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