Datasheet

HTU1 FTU HTU2
Peripheral Interconnect Subsystem
CRC2
PCR2
PCR3
EMAC
Slaves
DCAN1
DCAN2
DCAN3
MibSPI1
IOMM
PMM
Lockstep
VIMs
RTI
DCC1
DMA
EMIF
eQEP
1,2
eCAP
1..6
ePWM
1..7
NMPU
EMAC
DCAN4
PCR1
EMIF
Slave
CPU Interconnect Subsystem
Dual Cortex -R5F
CPUs in lockstep
32kB Icache
& Dcache w /
ECC
POM
4MB Flash
&
128kB
Flash for
EEPROM
Emulation
w/ ECC
512kB
SRAM
w/
ECC
NMPU
NMPU
STC1
EPC
SCM
SYS
DCC2
STC2
DMM
DAP
CCM-
R5F
MibSPI2
MibSPI3
MibSPI4
LIN1/SCI1
LIN2/SCI2
SCI3
SCI4
I2C1
I2C2
FlexRay
GIO
N2HET1
N2HET2
MibADC 1
MibADC 2
ESM
MibSPI5
CRC1
Dma_portA
uSCU
SDC MMR
Acp_s sram
Flash
portB
Flash
portA emif
pomPs_scr_m
Dma
portA
Axi-mAcp_m
Axi-pp Dma portB dap dmm htu1 ftu htu2 emac
crc2crc1pcr3Sdc mmr portpcr2pcr1Ps_scr_s
www.ti.com Introduction
Figure 2-1. Architectural Block Diagram
111
SPNU563–May 2014 Architecture
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