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36-14. DMM Direct Data Mode Destination Register (DMMDDMDEST) Field Descriptions........................... 2068
36-15. DMM Direct Data Mode Blocksize Register (DMMDDMBL) Field Descriptions................................. 2068
36-16. DMM Direct Data Mode Pointer Register (DMMDDMPT) Field Descriptions ................................... 2069
36-17. DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) Field Descriptions .......................... 2069
36-18. DMM Destination x Region 1 (DMMDESTxREG1) Field Descriptions ........................................... 2070
36-19. DMM Destination x Blocksize 1 (DMMDESTxBL1) Field Descriptions........................................... 2071
36-20. DMM Destination x Region 2 (DMMDESTxREG2) Field Descriptions ........................................... 2072
36-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) Field Descriptions........................................... 2073
36-22. DMM Pin Control 0 (DMMPC0) Field Descriptions ................................................................. 2074
36-23. DMM Pin Control 1 (DMMPC1) Field Descriptions ................................................................. 2075
36-24. DMM Pin Control 2 (DMMPC2) Field Descriptions ................................................................. 2077
36-25. DMM Pin Control 3 (DMMPC3) Field Descriptions ................................................................. 2078
36-26. DMM Pin Control 4 (DMMPC4) Field Descriptions ................................................................. 2079
36-27. DMM Pin Control 5 (DMMPC5) Field Descriptions ................................................................. 2081
36-28. DMM Pin Control 6 (DMMPC6) Field Descriptions ................................................................. 2082
36-29. DMM Pin Control 7 (DMMPC7) Field Descriptions ................................................................. 2084
36-30. DMM Pin Control 8 (DMMPC8) Field Descriptions ................................................................. 2085
37-1. Encoding of RAM Bits in Trace Mode Packet Format.............................................................. 2091
37-2. Encoding of Status Bits in Trace Mode Packet Format ............................................................ 2091
37-3. Encoding of SIZE bits in Trace Mode Packet Format .............................................................. 2091
37-4. Encoding of REG in Trace Mode Packet Format ................................................................... 2091
37-5. Number of Transfers/Packet........................................................................................... 2091
37-6. RTP Signals.............................................................................................................. 2094
37-7. RTP Control Registers.................................................................................................. 2096
37-8. RTP Global Control Register (RTPGLBCTRL) Field Descriptions................................................ 2097
37-9. FIFO Corresponding Addresses....................................................................................... 2099
37-10. Pins Used for Data Communication .................................................................................. 2099
37-11. RTP Trace Enable Register (RTPTRENA) Field Descriptions .................................................... 2100
37-12. RTP Global Status Register (RTPGSR) Field Descriptions ....................................................... 2102
37-13. RTP RAM 1 Trace Region Registers (RTPRAM1REGn) Field Descriptions.................................... 2104
37-14. RTP RAM 2 Trace Region Registers (RTPRAM2REGn) Field Descriptions.................................... 2105
37-15. RTP RAM 3 Trace Region Registers (RTPRAM3REGn) Field Descriptions.................................... 2106
37-16. RTP Peripheral Trace Region Registers (RTPPERREGn) Field Descriptions.................................. 2108
37-17. RTP Direct Data Mode Write Register (RTPDDMW) Field Descriptions ........................................ 2109
37-18. RTP Pin Control 0 Register (RTPPC0) Field Descriptions ........................................................ 2110
37-19. RTP Pin Control 1 Register (RTPPC1) Field Descriptions ........................................................ 2111
37-20. RTP Pin Control 2 Register (RTPPC2) Field Descriptions ........................................................ 2112
37-21. RTP Pin Control 3 Register (RTPPC3) Field Descriptions ........................................................ 2113
37-22. RTP Pin Control 4 Register (RTPPC4) Field Descriptions ........................................................ 2114
37-23. RTP Pin Control 5 Register (RTPPC5) Field Descriptions ........................................................ 2115
37-24. RTP Pin Control 6 Register (RTPPC6) Field Descriptions ........................................................ 2116
37-25. RTP Pin Control 7 Register (RTPPC7) Field Descriptions ........................................................ 2118
37-26. RTP Pin Control 8 Register (RTPPC8) Field Descriptions ........................................................ 2119
38-1. ESM Signals Set by eFuse Controller ................................................................................ 2121
38-2. eFuse Controller Registers............................................................................................. 2124
38-3. EFC Boundary Register (EFCBOUND) Field Descriptions ....................................................... 2124
38-4. EFC Pins Register (EFCPINS) Field Descriptions.................................................................. 2126
38-5. EFC Error Status Register (EFCERRSTAT) Field Descriptions .................................................. 2127
38-6. EFC Self Test Cycles Register (EFCSTCY) Field Descriptions .................................................. 2127
100
List of Tables SPNU563–May 2014
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