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32-56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions......................... 1829
32-57. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions ....................... 1829
32-58. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions..................................... 1830
32-59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions............................... 1830
32-60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions .............................................................................................................. 1831
32-61. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions................................... 1833
32-62. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions...................................... 1834
32-63. Receive Maximum Length Register (RXMAXLEN) Field Descriptions........................................... 1834
32-64. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ...................................... 1835
32-65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions...... 1835
32-66. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............. 1836
32-67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions .................... 1836
32-68. MAC Control Register (MACCONTROL) Field Descriptions ...................................................... 1837
32-69. MAC Status Register (MACSTATUS) Field Descriptions .......................................................... 1839
32-70. Emulation Control Register (EMCONTROL) Field Descriptions .................................................. 1841
32-71. FIFO Control Register (FIFOCONTROL) Field Descriptions ...................................................... 1841
32-72. MAC Configuration Register (MACCONFIG) Field Descriptions.................................................. 1842
32-73. Soft Reset Register (SOFTRESET) Field Descriptions ............................................................ 1842
32-74. MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions........................... 1843
32-75. MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions ........................... 1843
32-76. MAC Hash Address Register 1 (MACHASH1) Field Descriptions................................................ 1844
32-77. MAC Hash Address Register 2 (MACHASH2) Field Descriptions................................................ 1844
32-78. Back Off Test Register (BOFFTEST) Field Descriptions .......................................................... 1845
32-79. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ................................... 1845
32-80. Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................. 1846
32-81. Transmit Pause Timer Register (TXPAUSE) Field Descriptions.................................................. 1846
32-82. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions.......................................... 1847
32-83. MAC Address High Bytes Register (MACADDRHI) Field Descriptions .......................................... 1848
32-84. MAC Index Register (MACINDEX) Field Descriptions ............................................................. 1848
32-85. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions .................. 1849
32-86. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions................... 1849
32-87. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions................................. 1850
32-88. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ................................. 1850
33-1. ECAP Control and Status Registers .................................................................................. 1879
33-2. Time-Stamp Counter Register (TSCTR) Field Descriptions ....................................................... 1879
33-3. Counter Phase Control Register (CTRPHS) Field Descriptions .................................................. 1879
33-4. Capture-1 Register (CAP1) Field Descriptions ...................................................................... 1880
33-5. Capture-2 Register (CAP2) Field Descriptions ...................................................................... 1880
33-6. Capture-3 Register (CAP3) Field Descriptions ...................................................................... 1881
33-7. Capture-4 Register (CAP4) Field Descriptions ...................................................................... 1881
33-8. ECAP Control Register 2 (ECCTL2) Field Descriptions ........................................................... 1882
33-9. ECAP Control Register 1 (ECCTL1) Field Descriptions ........................................................... 1884
33-10. ECAP Interrupt Flag Register (ECFLG) Field Descriptions........................................................ 1886
33-11. ECAP Interrupt Enable Register (ECEINT) Field Descriptions.................................................... 1887
33-12. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions ................................................... 1888
33-13. ECAP Interrupt Clear Register (ECCLR) Field Descriptions ...................................................... 1889
34-1. EQEP Memory Map .................................................................................................... 1895
34-2. Quadrature Decoder Truth Table ..................................................................................... 1897
97
SPNU563–May 2014 List of Tables
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