Datasheet
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30-28. SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions .................................................... 1695
30-29. SCI Pin I/O Control Register 6 (SCIPIO6) Field Descriptions..................................................... 1696
30-30. SCI Pin I/O Control Register 7 (SCIPIO7) Field Descriptions..................................................... 1697
30-31. SCI Pin I/O Control Register 8 (SCIPIO8) Field Descriptions .................................................... 1697
30-32. Input/Output Error Enable Register (IODFTCTRL) Field Descriptions ........................................... 1698
30-33. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ........................................... 1701
31-1. Ways to Generate a NACK Bit ........................................................................................ 1710
31-2. Interrupt Requests Generated by I2C Module....................................................................... 1715
31-3. I2C Control Registers................................................................................................... 1718
31-4. I2C Own Address Manager Register (I2COAR) Field Descriptions .............................................. 1719
31-5. Correct Mode for OA Bits .............................................................................................. 1719
31-6. I2C Interrupt Mask Register (I2CIMR) Field Descriptions.......................................................... 1720
31-7. I2C Status Register (I2CSTR) Field Descriptions................................................................... 1721
31-8. I2C Clock Divider Low Register (I2CCKL) Field Descriptions..................................................... 1724
31-9. I2C Clock Control High Register (I2CCKH) Field Descriptions ................................................... 1724
31-10. I2C Data Count Register (I2CCNT) Field Descriptions............................................................. 1725
31-11. I2C Data Receive Register (I2CDRR) Field Descriptions.......................................................... 1725
31-12. I2C Slave Address Register (I2CSAR) Field Descriptions......................................................... 1726
31-13. Correct Mode for SA Bits............................................................................................... 1726
31-14. I2C Data Transmit Register (I2CDXR) Field Descriptions ......................................................... 1726
31-15. I2C Mode Register (I2CMDR) Field Descriptions ................................................................... 1727
31-16. I2C Module Condition, Bus Activity, and Mode...................................................................... 1729
31-17. I2C Module Operating Modes ......................................................................................... 1729
31-18. Number of Bits Sent on Bus ........................................................................................... 1729
31-19. I2C Interrupt Vector Register (I2CIVR) Field Descriptions......................................................... 1730
31-20. Interrupt Codes for INTCODE Bits.................................................................................... 1730
31-21. I2C Extended Mode Register (I2CEMDR) Field Descriptions ..................................................... 1731
31-22. I2C Prescale Register (I2CPSC) Field Descriptions................................................................ 1731
31-23. I2C Peripheral ID Register 1 (I2CPID1) Field Descriptions........................................................ 1732
31-24. I2C Peripheral ID Register 2 (I2CPID2) Field Descriptions........................................................ 1732
31-25. I2C DMA Control Register (I2CDMACR) Field Descriptions ...................................................... 1733
31-26. I2C Pin Function Register (I2CPFNC) Field Descriptions ......................................................... 1733
31-27. I2C Pin Direction Register (I2CPDIR) Field Descriptions .......................................................... 1734
31-28. I2C Data Input Register (I2CDIN) Field Descriptions............................................................... 1734
31-29. I2C Data Output Register (I2CDOUT) Field Descriptions.......................................................... 1735
31-30. I2C Data Set Register (I2CDSET) Field Description ............................................................... 1735
31-31. I2C Data Clear Register (I2CDSET) Field Descriptions............................................................ 1736
31-32. I2C Pin Open Drain Register (I2CPDR) Field Descriptions........................................................ 1736
31-33. I2C Pull Disable Register (I2CPDIS) Field Descriptions ........................................................... 1737
31-34. I2C Pull Select Register (I2CPSEL) Field Descriptions ............................................................ 1737
31-35. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ........................................... 1738
31-36. I2C Pins Slew Rate Select Register (I2CSRS) Field Descriptions................................................ 1738
32-1. EMAC and MDIO Signals for MII Interface .......................................................................... 1745
32-2. EMAC and MDIO Signals for RMII Interface ........................................................................ 1746
32-3. MDIO Multiplexing Control ............................................................................................. 1747
32-4. MII/RMII Multiplexing Control .......................................................................................... 1747
32-5. Ethernet Frame Description............................................................................................ 1748
32-6. Basic Descriptor Description........................................................................................... 1750
32-7. Receive Frame Treatment Summary ................................................................................. 1775
95
SPNU563–May 2014 List of Tables
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