Datasheet

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28-41. TG Control Registers (TGxCTRL) Field Descriptions .............................................................. 1521
28-42. DMA Channel Control Register (DMAxCTRL) Field Descriptions ................................................ 1524
28-43. MibSPI DMAxCOUNT Register (ICOUNT) Field Descriptions .................................................... 1526
28-44. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions ......................................... 1527
28-45. MibSPI Parity/ECC Control Register (PAR_ECC_CTRL) Field Descriptions ................................... 1528
28-46. Parity/ECC Status Register (PAR_ECC_STAT) Field Descriptions .............................................. 1529
28-47. Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1) Field
Descriptions .............................................................................................................. 1530
28-48. Effect of BIG_ENDIAN Port on UERRADDR1[1:0] Bits ............................................................ 1531
28-49. Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) Field
Descriptions .............................................................................................................. 1532
28-50. Effect of BIG_ENDIAN Port on UERRADDR0[1:0] Bits ............................................................ 1533
28-51. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions ...................... 1533
28-52. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions....................................... 1534
28-53. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions........................... 1536
28-54. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions........................... 1538
28-55. ECC Diagnostic Control Register (ECCDIAG_CTRL) Field Descriptions........................................ 1539
28-56. ECC Diagnostic Status Register (ECCDIAG_STAT) Field Descriptions......................................... 1540
28-57. Single Bit Error Address Register - RXRAM (SBERRADDR1) Field Descriptions ............................. 1541
28-58. Single Bit Error Address Register - TXRAM (SBERRADDR0) Field Descriptions.............................. 1542
28-59. Multi-buffer RAM Register.............................................................................................. 1544
28-60. Multi-buffer RAM Transmit Data Register Field Descriptions...................................................... 1545
28-61. Multi-buffer Receive Buffer Register Field Descriptions............................................................ 1547
29-1. Superfractional Bit Modulation for SCI Mode (Normal Configuration) ........................................... 1566
29-2. Superfractional Bit Modulation for SCI Mode (Maximum Configuration) ........................................ 1567
29-3. SCI Mode (Minimum Configuration) .................................................................................. 1567
29-4. SCI/LIN Interrupts ....................................................................................................... 1574
29-5. Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than 1.3..................... 1581
29-6. Response Length with SCIFORMAT[18:16] Programming ........................................................ 1581
29-7. Superfractional Bit Modulation for LIN Master Mode and Slave Mode .......................................... 1583
29-8. Timeout Values in T
bit
Units ............................................................................................ 1590
29-9. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ........................................... 1603
29-10. SCI/LIN Control Registers.............................................................................................. 1604
29-11. SCI Global Control Register 0 (SCIGCR0) Field Descriptions .................................................... 1605
29-12. SCI Global Control Register 1 (SCIGCR1) Field Descriptions .................................................... 1606
29-13. SCI Receiver Status Flags ............................................................................................. 1609
29-14. SCI Transmitter Status Flags .......................................................................................... 1609
29-15. SCI Global Control Register 2 (SCIGCR2) Field Descriptions .................................................... 1610
29-16. SCI Set Interrupt Register (SCISETINT) Field Descriptions....................................................... 1612
29-17. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions................................................. 1615
29-18. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions........................................... 1618
29-19. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions .................................... 1621
29-20. SCI Flags Register (SCIFLR) Field Descriptions.................................................................... 1624
29-21. SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................ 1631
29-22. SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................ 1631
29-23. SCI Format Control Register (SCIFORMAT) Field Descriptions.................................................. 1632
29-24. Baud Rate Selection Register (BRS) Field Descriptions........................................................... 1633
29-25. Comparative Baud Values for Different P Values, Asynchronous Mode ........................................ 1634
29-26. Receiver Emulation Data Buffer (SCIED) Field Descriptions...................................................... 1635
93
SPNU563–May 2014 List of Tables
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