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27-26. IF1/IF2 Arbitration Register Field Descriptions ...................................................................... 1425
27-27. IF1/IF2 Message Control Register Field Descriptions.............................................................. 1427
27-28. IF3 Observation Register (DCAN IF3OBS) Field Descriptions.................................................... 1429
27-29. IF3 Mask Register (DCAN IF3MSK) Field Descriptions............................................................ 1431
27-30. IF3 Arbitration Register (DCAN IF3ARB) Field Descriptions ...................................................... 1432
27-31. IF3 Message Control Register (DCAN IF3MCTL) Field Descriptions ............................................ 1433
27-32. IF3 Update Control Register Field Descriptions..................................................................... 1435
27-33. CAN TX IO Control Register (DCAN TIOC) Field Descriptions ................................................... 1436
27-34. CAN RX IO Control Register (DCAN RIOC) Field Descriptions .................................................. 1437
28-1. Pin Configurations....................................................................................................... 1441
28-2. MibSPI/SPI Configurations............................................................................................. 1442
28-3. Clocking Modes.......................................................................................................... 1454
28-4. Pin Mapping for SIMO Pin with MSB First ........................................................................... 1463
28-5. Pin Mapping for SOMI Pin with MSB First ........................................................................... 1463
28-6. Pin Mapping for SIMO Pin with LSB First............................................................................ 1464
28-7. Pin Mapping for SOMI Pin with LSB First............................................................................ 1464
28-8. SPI Registers ............................................................................................................ 1477
28-9. SPI Global Control Register 0 (SPIGCR0) Field Descriptions .................................................... 1478
28-10. SPI Global Control Register 1 (SPIGCR1) Field Descriptions .................................................... 1479
28-11. SPI Interrupt Register (SPIINT0) Field Descriptions................................................................ 1480
28-12. SPI Interrupt Level Register (SPILVL) Field Descriptions ......................................................... 1482
28-13. SPI Flag Register (SPIFLG) Field Descriptions ..................................................................... 1483
28-14. SPI Pin Control (SPIPC0) Field Descriptions........................................................................ 1486
28-15. SPI Pin Control Register (SPIPC1) Field Descriptions............................................................. 1487
28-16. SPI Pin Control Register 2 (SPIPC2) Field Descriptions........................................................... 1489
28-17. SPI Pin Control Register 3 (SPIPC3) Field Descriptions........................................................... 1490
28-18. SPI Pin Control Register 4 (SPIPC4) Field Descriptions........................................................... 1491
28-19. SPI Pin Control Register 5 (SPIPC5) Field Descriptions........................................................... 1493
28-20. SPI Pin Control Register 6 (SPIPC6) Field Descriptions........................................................... 1495
28-21. SPI Pin Control Register 7 (SPIPC7) Field Descriptions........................................................... 1496
28-22. SPI Pin Control Register 8 (SPIPC8) Field Descriptions........................................................... 1497
28-23. SPI Transmit Data Register 0 (SPIDAT0) Field Descriptions ..................................................... 1498
28-24. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions ..................................................... 1499
28-25. SPI Receive Buffer Register (SPIBUF) Field Descriptions ........................................................ 1500
28-26. SPI Emulation Register (SPIEMU) Field Descriptions.............................................................. 1502
28-27. SPI Delay Register (SPIDELAY) Field Descriptions................................................................ 1502
28-28. SPI Default Chip Select Register (SPIDEF) Field Descriptions................................................... 1505
28-29. SPI Data Format Registers (SPIFMTn) Field Descriptions ........................................................ 1506
28-30. Transfer Group Interrupt Vector 0 (INTVECT0) ..................................................................... 1508
28-31. Transfer Group Interrupt Vector 1 (INTVECT1) ..................................................................... 1509
28-32. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions................................. 1511
28-33. Multi-buffer Mode Enable Register (MIBSPIE) Field Descriptions................................................ 1513
28-34. TG Interrupt Enable Set Register (TGITENST) Field Descriptions ............................................... 1514
28-35. TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions ............................................ 1515
28-36. Transfer Group Interrupt Level Set Register (TGITLVST) Field Descriptions................................... 1516
28-37. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions................................ 1517
28-38. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions................................ 1518
28-39. Tick Count Register (TICKCNT) Field Descriptions ................................................................ 1519
28-40. Last TG End Pointer (LTGPEND) Field Descriptions .............................................................. 1520
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List of Tables SPNU563–May 2014
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