Datasheet

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26-148. Message Handler Status (MHDS) Field Descriptions ............................................................. 1333
26-149. Last Dynamic Transmit Slot (LDTS) Field Descriptions .......................................................... 1334
26-150. FIFO Status Register (FSR) Field Descriptions.................................................................... 1335
26-151. Message Handler Constraint Flags (MHDF) Field Descriptions ................................................. 1336
26-152. Transmission Request Registers (TXRQn) Field Description.................................................... 1338
26-153. New Data Registers (NDATn) Field Descriptions.................................................................. 1340
26-154. Message Buffer Status Changed Registers (MBSCn) Field Descriptions...................................... 1341
26-155. Core Release Register (CREL) Field Descriptions ................................................................ 1342
26-156. Release Coding ........................................................................................................ 1342
26-157. Endian Register (ENDN) Field Descriptions........................................................................ 1342
26-158. Write Data Section Registers (WRDSn) Field Descriptions ...................................................... 1343
26-159. Write Header Section Register 1 (WRHS1) Field Descriptions.................................................. 1344
26-160. Channel Filter Control Bit Descriptions ............................................................................. 1345
26-161. Write Header Section Register 2 (WRHS2) Field Descriptions.................................................. 1345
26-162. Write Header Section Register 3 (WRHS3) Field Descriptions.................................................. 1346
26-163. Input Buffer Command Mask Register (IBCM) Field Descriptions .............................................. 1347
26-164. Input Buffer Command Request Register (IBCR) Field Descriptions ........................................... 1348
26-165. Read Data Section Registers (RDDSn) Field Descriptions ...................................................... 1349
26-166. Read Header Section Register 1 (RDHS1) Field Descriptions .................................................. 1350
26-167. Read Header Section Register 2 (RDHS2) Field Descriptions .................................................. 1351
26-168. Read Header Section Register 3 (RDHS3) Field Descriptions .................................................. 1352
26-169. Message Buffer Status Register (MBS) Field Descriptions ...................................................... 1353
26-170. Output Buffer Command Mask Register (MBS) Field Descriptions ............................................. 1356
26-171. Output Buffer Command Mask Register (OBCR) Field Descriptions ........................................... 1357
27-1. Parameters of the CAN Bit Time ...................................................................................... 1363
27-2. Message Object Field Descriptions................................................................................... 1370
27-3. Message RAM Addressing in Debug/Suspend and RDA Mode .................................................. 1372
27-4. Message Interface Register Sets 1 and 2 ........................................................................... 1375
27-5. Message Interface Register 3 ......................................................................................... 1377
27-6. DCAN Control Registers ............................................................................................... 1396
27-7. CAN Control Register (DCAN CTL) Field Descriptions ............................................................ 1398
27-8. Error and Status Register (DCAN ES) Field Descriptions ......................................................... 1401
27-9. Error Counter Register (DCAN ERRC) Field Descriptions......................................................... 1403
27-10. Bit Timing Register (DCAN BTR) Field Descriptions ............................................................... 1404
27-11. Interrupt Register (DCAN INT) Field Descriptions .................................................................. 1405
27-12. Test Register (DCAN TEST) Field Descriptions .................................................................... 1406
27-13. Parity Error Code Register (DCAN PERR) Field Descriptions .................................................... 1407
27-14. ECC Diagnostic Register (DCAN ECCDIAG) Field Descriptions ................................................. 1407
27-15. ECC Diagnostic Status Register (DCAN ECCDIAG STAT) Field Descriptions ................................. 1408
27-16. ECC Control and Status Register (DCAN ECC CS) Field Descriptions ......................................... 1409
27-17. ECC Single Bit Error Code Register (DCAN ECC SERR) Field Descriptions................................... 1410
27-18. Auto-Bus-On Time Register (DCAN ABOTR) Field Descriptions................................................. 1411
27-19. Transmission Request Registers Field Descriptions ............................................................... 1412
27-20. New Data Registers Field Descriptions .............................................................................. 1414
27-21. Interrupt Pending Registers Field Descriptions...................................................................... 1416
27-22. Message Valid Registers Field Descriptions......................................................................... 1418
27-23. Interrupt Multiplexer Registers Field Descriptions .................................................................. 1419
27-24. IF1/IF2 Command Register Field Descriptions...................................................................... 1421
27-25. IF1/IF2 Mask Register Field Descriptions............................................................................ 1423
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SPNU563–May 2014 List of Tables
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