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24-24. Interrupt Offset Register 0 (HTU INTOFF0) Field Descriptions ................................................... 1101
24-25. Interrupt Offset Register 1 (HTU INTOFF1) Field Descriptions ................................................... 1102
24-26. Buffer Initialization Mode Register (HTU BIM) Field Descriptions ................................................ 1103
24-27. Buffer Initialization....................................................................................................... 1103
24-28. Request Lost Flag Register (HTU RLOSTFL) Field Descriptions ................................................ 1105
24-29. Buffer Full Interrupt Flag Register (HTU BFINTFL) Field Descriptions .......................................... 1105
24-30. BER Interrupt Flag Register (HTU BERINTFL) Field Descriptions ............................................... 1106
24-31. Memory Protection 1 Start Address Register (HTU MP1S) Field Descriptions ................................. 1107
24-32. Memory Protection 1 End Address Register (HTU MP1E) Field Descriptions .................................. 1107
24-33. Debug Control Register (HTU DCTRL) Field Descriptions ........................................................ 1108
24-34. Watch Point Register (HTU WPR) Field Descriptions.............................................................. 1109
24-35. Watch Mask Register (HTU WMR) Field Descriptions ............................................................. 1109
24-36. Module Identification Register (HTU ID) Field Descriptions ....................................................... 1110
24-37. Parity Control Register (HTU PCR) Field Descriptions............................................................. 1111
24-38. Parity Address Register (HTU PAR) Field Descriptions ........................................................... 1112
24-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions ............................. 1113
24-40. Memory Protection 0 Start address Register (HTU MP0S) Field Descriptions ................................. 1116
24-41. Memory Protection End Address Register (HTU MP0E) Field Descriptions .................................... 1116
24-42. Double Control Packet Memory Map ................................................................................. 1117
24-43. Initial Full Address A Register (HTU IFADDRA) Field Descriptions .............................................. 1118
24-44. Initial Full Address B Register (HTU IFADDRB) Field Descriptions .............................................. 1118
24-45. Initial NHET Address and Control Register (HTU IHADDRCT) Field Descriptions............................. 1119
24-46. Initial Transfer Count Register (HTU ITCOUNT) Field Descriptions ............................................. 1120
24-47. Current Full Address A Register (HTU CFADDRA) Field Descriptions .......................................... 1121
24-48. Current Full Address B Register (HTU CFADDRB) Field Descriptions .......................................... 1122
24-49. Initial Transfer Count Register (HTU CFCOUNT) Field Descriptions ............................................ 1123
24-50. Application Examples for Setting the Transfer Modes of CP A and B of a DCP ............................... 1124
25-1. GIO Control Registers .................................................................................................. 1133
25-2. GIO Global Control Register (GIOGCR0) Field Descriptions ..................................................... 1134
25-3. GIO Interrupt Detect Register (GIOINTDET) Field Descriptions.................................................. 1135
25-4. GIO Interrupt Polarity Register (GIOPOL) Field Descriptions ..................................................... 1136
25-5. GIO Interrupt Enable Set Register (GIOENASET) Field Descriptions ........................................... 1137
25-6. GIO Interrupt Enable Clear Register (GIOENACLR) Field Descriptions......................................... 1138
25-7. GIO Interrupt Priority Register (GIOLVLSET) Field Descriptions ................................................. 1139
25-8. GIO Interrupt Priority Register (GIOLVLCLR) Field Descriptions................................................. 1141
25-9. GIO Interrupt Flag Register (GIOFLG) Field Descriptions ......................................................... 1142
25-10. GIO Offset 1 Register (GIOOFF1) Field Descriptions .............................................................. 1143
25-11. GIO Offset 2 Register (GIOOFF2) Field Descriptions .............................................................. 1144
25-12. GIO Emulation 1 Register (GIOEMU1) Field Descriptions ........................................................ 1145
25-13. GIO Emulation 2 Register (GIOEMU2) Field Descriptions ........................................................ 1146
25-14. GIO Data Direction Registers (GIODIR[A-B]) Field Descriptions ................................................. 1147
25-15. GIO Data Input Registers (GIODIN[A-B]) Field Descriptions...................................................... 1147
25-16. GIO Data Output Registers (GIODOUT[A-B]) Field Descriptions................................................. 1148
25-17. GIO Data Set Registers (GIODSET[A-B]) Field Descriptions ..................................................... 1148
25-18. GIO Data Clear Registers (GIODCLR[A-B]) Field Descriptions................................................... 1149
25-19. GIO Open Drain Registers (GIOPDR[A-B]) Field Descriptions ................................................... 1149
25-20. GIO Pull Disable Registers (GIOPULDIS[A-B]) Field Descriptions .............................................. 1150
25-21. GIO Pull Select Registers (GIOPSL[A-B]) Field Descriptions ..................................................... 1150
25-22. Output Buffer, and Pull Control Behavior for GIO Pins ............................................................ 1151
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SPNU563–May 2014 List of Tables
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