Datasheet

www.ti.com
22-34. ADC Event Group Status Register (ADEVSR) Field Descriptions ................................................. 902
22-35. ADC Group1 Status Register (ADG1SR) Field Descriptions ....................................................... 903
22-36. ADC Group2 Status Register (ADG2SR) Field Descriptions ....................................................... 904
22-37. ADC Event Group Channel Select Register (ADEVSEL) Field Descriptions ..................................... 905
22-38. ADC Group1 Channel Select Register (ADG1SEL) Field Descriptions ........................................... 906
22-39. ADC Group2 Channel Select Register (ADG2SEL) Field Descriptions ........................................... 907
22-40. ADC Calibration and Error Offset Correction Register (ADCALR) Field Descriptions........................... 908
22-41. ADC State Machine Status Register (ADSMSTATE) Field Descriptions ......................................... 908
22-42. ADC Channel Last Conversion Value Register (ADLASTCONV) Field Descriptions............................ 909
22-43. ADC Event Group Results' FIFO Register (ADEVBUFFER) Field Descriptions ................................. 910
22-44. ADC Group1 Results FIFO Register (ADG1BUFFER) Field Descriptions ........................................ 911
22-45. ADC Group2 Results FIFO Register (ADG2BUFFER) Field Descriptions ........................................ 912
22-46. ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) Field Descriptions ............... 913
22-47. ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) Field Descriptions ..................... 914
22-48. ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) Field Descriptions ..................... 915
22-49. ADC ADEVT Pin Direction Control Register (ADEVTDIR) Field Descriptions.................................... 916
22-50. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) Field Descriptions ............................. 917
22-51. ADC ADEVT Pin Input Value Register (ADEVTIN) Field Descriptions ............................................ 917
22-52. ADC ADEVT Pin Set Register (ADEVTSET) Field Descriptions ................................................... 918
22-53. ADC ADEVT Pin Clear Register (ADEVTCLR) Field Descriptions................................................. 918
22-54. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) Field Descriptions................................ 919
22-55. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) Field Descriptions .............................. 919
22-56. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) Field Descriptions ............................... 920
22-57. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) Field Descriptions ....... 920
22-58. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) Field Descriptions.............. 921
22-59. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) Field Descriptions.............. 922
22-60. ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) Field Descriptions .................. 924
22-61. ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK) Field Descriptions................. 925
22-62. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) Field Descriptions.......... 926
22-63. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) Field Descriptions ....... 926
22-64. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) Field Descriptions ....................... 927
22-65. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) Field Descriptions ..................... 927
22-66. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) Field Descriptions .................. 928
22-67. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) Field Descriptions ........................ 928
22-68. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) Field Descriptions ........................ 929
22-69. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) Field Descriptions................... 929
22-70. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) Field Descriptions......................... 930
22-71. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) Field Descriptions......................... 930
22-72. ADC Parity Control Register (ADPARCR) Field Descriptions ...................................................... 931
22-73. ADC Parity Error Address Register (ADPARADDR) Field Descriptions........................................... 932
22-74. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) Field Descriptions ............................ 932
22-75. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) Field
Descriptions ............................................................................................................... 933
22-76. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) Field Descriptions.. 933
22-77. ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) Field Descriptions.. 934
22-78. ADC Event Group Current Count Register (ADEVCURRCOUNT) Field Descriptions .......................... 935
22-79. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) Field Descriptions.......................... 935
22-80. ADC Group1 Current Count Register (ADG1CURRCOUNT) Field Descriptions ................................ 936
22-81. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) Field Descriptions................................ 936
84
List of Tables SPNU563–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated