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21-28. SDRAM Refresh Control Register (SDRCR) Field Descriptions ................................................... 816
21-29. Asynchronous n Configuration Register (CEnCFG) Field Descriptions ........................................... 817
21-30. SDRAM Timing Register (SDTIMR) Field Descriptions.............................................................. 818
21-31. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions...................................... 819
21-32. EMIF Interrupt Raw Register (INTRAW) Field Descriptions ........................................................ 820
21-33. EMIF Interrupt Mask Register (INTMSK) Field Descriptions........................................................ 821
21-34. EMIF Interrupt Mask Set Register (INTMSKSET) Field Descriptions.............................................. 822
21-35. EMIF Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions ........................................... 823
21-36. Page Mode Control Register (PMCR) Field Descriptions ........................................................... 824
21-37. SR Field Value For the EMIF to K4S641632H-TC(L)70 Interface ................................................. 825
21-38. SDTIMR Field Calculations for the EMIF to K4S641632H-TC(L)70 Interface .................................... 827
21-39. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface .................................................. 828
21-40. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface .................................................. 828
21-41. SDCR Field Values For the EMIF to K4S641632H-TC(L)70 Interface ............................................ 829
21-42. AC Characteristics for a Read Access................................................................................. 830
21-43. AC Characteristics for a Write Access ................................................................................. 830
22-1. ADC Look-Up Table Field Descriptions................................................................................ 847
22-2. Calibration Reference Voltages......................................................................................... 857
22-3. Self-Test Reference Voltages........................................................................................... 860
22-4. Determination of ADC Input Channel Condition ...................................................................... 861
22-5. Output Buffer and Pull Control Behavior for ADxEVT as GPIO Pins .............................................. 865
22-6. ADC Registers ............................................................................................................ 866
22-7. ADC Reset Control Register (ADRSTCR) Field Descriptions ...................................................... 868
22-8. ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions ................................... 868
22-9. ADC Clock Control Register (ADCLOCKCR) Field Descriptions................................................... 870
22-10. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions ........................................ 871
22-11. ADC Event Group Operating Mode Control Register (ADEVMODECR) Field Descriptions.................... 873
22-12. ADC Group1 Operating Mode Control Register (ADG1MODECR) Field Descriptions.......................... 876
22-13. ADC Group 2 Operating Mode Control Register (ADG2MODECR) Field Descriptions ......................... 879
22-14. ADC Event Group Trigger Source Select Register (ADEVSRC) Field Descriptions............................. 881
22-15. ADC Group1 Trigger Source Select Register (ADG1SRC) Field Descriptions................................... 882
22-16. ADC Group2 Trigger Source Select Register (ADG2SRC) Field Descriptions................................... 883
22-17. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions ...................... 884
22-18. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) Field Descriptions ............................ 885
22-19. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) Field Descriptions ............................ 886
22-20. ADC Event Group Interrupt Flag Register (ADEVINTFLG) Field Descriptions................................... 887
22-21. ADC Group1 Interrupt Flag Register (ADG1INTFLG) Field Descriptions ......................................... 888
22-22. ADC Group2 Interrupt Flag Register (ADG2INTFLG) Field Descriptions ......................................... 889
22-23. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) Field Descriptions .............. 890
22-24. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) Field Descriptions..................... 890
22-25. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) Field Descriptions..................... 891
22-26. ADC Event Group DMA Control Register (ADEVDMACR) Field Descriptions ................................... 892
22-27. ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions ......................................... 894
22-28. ADC Group2 DMA Control Register (ADG2DMACR) Field Descriptions ......................................... 896
22-29. ADC Results Memory Configuration Register (ADBNDCR) Field Descriptions .................................. 898
22-30. ADC Results Memory Size Configuration Register (ADBNDEND) Field Descriptions .......................... 899
22-31. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) Field Descriptions .................. 900
22-32. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) Field Descriptions ........................ 900
22-33. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) Field Descriptions ........................ 901
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SPNU563–May 2014 List of Tables
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