Datasheet

www.ti.com
20-89. DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) Field Descriptions................. 765
20-90. DMA Memory Protection Region 6 End Address Register (DMAMPR6E) Field Descriptions.................. 765
20-91. DMA Memory Protection Region 7 Start Address Register (DMAMPR7S) Field Descriptions................. 766
20-92. DMA Memory Protection Region 7 End Address Register (DMAMPR7E) Field Descriptions.................. 766
20-93. DMA Single Bit ECC Control Register (DMASECCCTRL) Field Description ..................................... 767
20-94. DMA ECC Single Bit Error Address Register (DMAECCSBE) Field Descriptions ............................... 768
20-95. FIFO A Status Register (FIFOASTAT) Field Descriptions .......................................................... 769
20-96. FIFO B Status Register (FIFOBSTAT) Field Descriptions .......................................................... 769
20-97. DMA Request Polarity Select Register (DMAREQPS1) Field Descriptions....................................... 770
20-98. DMA Request Polarity Select Register (DMAREQPS1) Field Descriptions....................................... 770
20-99. Transaction Parity Error Event Control Register (TERECTRL) Field Descriptions .............................. 771
20-100. TER Event Flag Register (TERFLAG) Field Descriptions.......................................................... 771
20-101. TER Event Channel Offset Register (TERROFFSET) Field Descriptions ....................................... 772
20-102. Initial Source Address Register (ISADDR) Field Descriptions..................................................... 773
20-103. Initial Destination Address Register (IDADDR) Field Descriptions ............................................... 773
20-104. Initial Transfer Count Register (ITCOUNT) Field Descriptions .................................................... 774
20-105. Channel Control Register (CHCTRL) Field Descriptions........................................................... 775
20-106. Element Index Offset Register (EIOFF) Field Descriptions ....................................................... 776
20-107. Frame Index Offset Register (FIOFF) Field Descriptions .......................................................... 776
20-108. Current Source Address Register (CSADDR) Field Descriptions ................................................ 777
20-109. Current Destination Address Register (CDADDR) Field Descriptions............................................ 777
20-110. Current Transfer Count Register (CTCOUNT) Field Descriptions ................................................ 777
21-1. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories ......................................... 781
21-2. EMIF Pins Specific to SDRAM .......................................................................................... 782
21-3. EMIF Pins Specific to Asynchronous Memory ........................................................................ 782
21-4. EMIF SDRAM Commands............................................................................................... 783
21-5. Truth Table for SDRAM Commands ................................................................................... 783
21-6. 16-bit EMIF Address Pin Connections ................................................................................. 785
21-7. Description of the SDRAM Configuration Register (SDCR)......................................................... 786
21-8. Description of the SDRAM Refresh Control Register (SDRCR).................................................... 786
21-9. Description of the SDRAM Timing Register (SDTIMR).............................................................. 787
21-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR) ...................................... 787
21-11. SDRAM LOAD MODE REGISTER Command........................................................................ 788
21-12. Refresh Urgency Levels ................................................................................................. 789
21-13. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM ................................................... 794
21-14. Normal Mode vs. Select Strobe Mode ................................................................................. 795
21-15. Description of the Asynchronous m Configuration Register (CEnCFG)........................................... 797
21-16. Description of the Asynchronous Wait Cycle Configuration Register (AWCC) .................................. 798
21-17. Description of the EMIF Interrupt Mask Set Register (INTMSKSET) .............................................. 798
21-18. Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR) ............................................ 798
21-19. Asynchronous Read Operation in Normal Mode ..................................................................... 799
21-20. Asynchronous Write Operation in Normal Mode ..................................................................... 801
21-21. Asynchronous Read Operation in Select Strobe Mode.............................................................. 803
21-22. Asynchronous Write Operation in Select Strobe Mode.............................................................. 805
21-23. Interrupt Monitor and Control Bit Fields................................................................................ 809
21-24. External Memory Interface (EMIF) Registers ......................................................................... 813
21-25. Module ID Register (MIDR) Field Descriptions ....................................................................... 813
21-26. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions................................. 814
21-27. SDRAM Configuration Register (SDCR) Field Descriptions ........................................................ 815
82
List of Tables SPNU563–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated