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19-15. Pending Interrupt Read Location Registers (INTREQ) Field Descriptions ........................................ 676
19-16. Interrupt Enable Set Registers (REQENASET) Field Descriptions ................................................ 677
19-17. Request Enable Clear Registers (REQENACLR) Field Descriptions ............................................. 678
19-18. Wake-Up Enable Set Registers (WAKEENASET) Field Descriptions ............................................. 679
19-19. Wake-Up Enable Clear Registers (WAKEENACLR) Field Descriptions........................................... 680
19-20. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions .................................................. 681
19-21. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions................................................... 681
19-22. Capture Event Register (CAPEVT) Field Descriptions .............................................................. 682
19-23. Interrupt Control Registers Organization .............................................................................. 683
19-24. Interrupt Control Registers (CHANCTRL[0:31]) Field Descriptions ................................................ 683
20-1. Arbitration According to Priority Queues and Priority Schemes .................................................... 695
20-2. Maximum Number of DMA Transactions per Channel in Non-Bypass Mode..................................... 703
20-3. Maximum Number of DMA Transactions per Channel in Bypass Mode .......................................... 703
20-4. ECC Mapping ............................................................................................................. 707
20-5. DMA Control Registers................................................................................................... 709
20-6. Control Packet Memory Map............................................................................................ 711
20-7. Global Control Register (GCTRL) Field Descriptions ................................................................ 712
20-8. Channel Pending Register (PEND) Field Descriptions .............................................................. 713
20-9. DMA Status Register (DMASTAT) Field Descriptions ............................................................... 713
20-10. DMA Revision ID Register Description ................................................................................ 714
20-11. HW Channel Enable Set and Status Register (HWCHENAS) Field Descriptions................................ 715
20-12. HW Channel Enable Reset and Status Register (HWCHENAR) Field Descriptions ............................ 715
20-13. SW Channel Enable Set and Status Register (SWCHENAS) Field Descriptions ................................ 716
20-14. SW Channel Enable Reset and Status Register (SWCHENAR) Field Descriptions............................. 716
20-15. Channel Priority Set Register (CHPRIOS) Field Descriptions ...................................................... 717
20-16. Channel Priority Reset Register (CHPRIOR) Field Descriptions ................................................... 717
20-17. Global Channel Interrupt Enable Set Register (GCHIENAS) Field Descriptions................................. 718
20-18. Global Channel Interrupt Enable Reset Register (GCHIENAR) Field Descriptions.............................. 718
20-19. DMA Request Assignment Register 0 (DREQASI0) Field Descriptions........................................... 719
20-20. DMA Request Assignment Register 1 (DREQASI1) Field Descriptions........................................... 720
20-21. DMA Request Assignment Register 2 (DREQASI2) Field Descriptions........................................... 721
20-22. DMA Request Assignment Register 3 (DREQASI3) Field Descriptions........................................... 722
20-23. DMA Request Assignment Register 4 (DREQASI4) Field Descriptions........................................... 723
20-24. DMA Request Assignment Register 5 (DREQASI5) Field Descriptions........................................... 724
20-25. DMA Request Assignment Register 6 (DREQASI6) Field Descriptions........................................... 725
20-26. DMA Request Assignment Register 7 (DREQASI7) Field Descriptions........................................... 726
20-27. Port Assignment Register 0 (PAR0) Field Descriptions ............................................................. 727
20-28. Port Assignment Register 1 (PAR1) Field Descriptions ............................................................. 728
20-29. Port Assignment Register 2 (PAR2) Field Descriptions ............................................................. 729
20-30. Port Assignment Register 3 (PAR3) Field Descriptions ............................................................. 730
20-31. FTC Interrupt Mapping Register (FTCMAP) Field Descriptions .................................................... 731
20-32. LFS Interrupt Mapping Register (LFSMAP) Field Descriptions..................................................... 731
20-33. HBC Interrupt Mapping Register (HBCMAP) Field Descriptions ................................................... 731
20-34. BTC Interrupt Mapping Register (BTCMAP) Field Descriptions.................................................... 732
20-35. BER Interrupt Mapping Register (BERMAP) Field Descriptions.................................................... 732
20-36. FTC Interrupt Enable Set Register (FTCINTENAS) Field Descriptions ........................................... 733
20-37. FTC Interrupt Enable Reset (FTCINTENAR) Field Descriptions ................................................... 733
20-38. LFS Interrupt Enable Set Register (LFSINTENAS) Field Descriptions ............................................ 734
20-39. LFS Interrupt Enable Reset Register (LFSINTENAR) Field Descriptions......................................... 734
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List of Tables SPNU563–May 2014
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