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13-16. CCM-R5F Key Register 4 (CCMKEYR4) Field Descriptions........................................................ 505
13-17. CCM-R5FPower Domain Status Register 0 (CCMPDSTAT0) Field Descriptions................................ 506
14-1. Valid Frequency Ranges for PLL ....................................................................................... 515
14-2. PLL Value Encoding...................................................................................................... 516
14-3. State Machine Timings................................................................................................... 520
14-4. PLL Module Registers.................................................................................................... 524
14-5. LPOCLKDET Module Registers ........................................................................................ 524
14-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions................................................ 525
14-7. SSW PLL BIST Control Register 2 (SSWPLL2) Field Descriptions................................................ 526
14-8. SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions................................................ 527
15-1. DCC Control Registers .................................................................................................. 539
15-2. DCC Control Register (DCCGCTRL) Field Descriptions ........................................................... 540
15-3. DCC Revision Id Register (DCCREV) Field Descriptions .......................................................... 541
15-4. DCC Counter0 Seed Register (DCCCNT0SEED) Field Descriptions ............................................. 541
15-5. DCC Valid0 Seed Register (DCCVALID0SEED) Field Descriptions .............................................. 542
15-6. DCC Counter1 Seed Register (DCCCNT0SEED) Field Descriptions ............................................. 542
15-7. DCC Status Register (DCCSTAT) Field Descriptions ............................................................... 543
15-8. DCC Counter0 Seed Register (DCCCNT0) Field Descriptions .................................................... 544
15-9. DCC Valid0 Value Register (DCCVALID0) Field Descriptions ..................................................... 545
15-10. DCC Counter1 Value Register (DCCCNT1) Field Descriptions ................................................... 545
15-11. DCC Counter1 Value Register (DCCCNT1) Field Descriptions ................................................... 546
15-12. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) Field Descriptions ................... 546
16-1. ESM Interrupt and ERROR Pin Behavior.............................................................................. 549
16-2. ESM Control Registers................................................................................................... 554
16-3. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) Field Descriptions .................. 555
16-4. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) Field Descriptions.................. 555
16-5. ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) Field Descriptions ................................... 556
16-6. ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) Field Descriptions................................. 556
16-7. ESM Interrupt Level Set/Status Register 1 (ESMILSR1) Field Descriptions...................................... 557
16-8. ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) Field Descriptions ................................... 557
16-9. ESM Status Register 1 (ESMSR1) Field Descriptions .............................................................. 558
16-10. ESM Status Register 2 (ESMSR2) Field Descriptions .............................................................. 558
16-11. ESM Status Register 3 (ESMSR3) Field Descriptions .............................................................. 559
16-12. ESM ERROR Pin Status Register (ESMEPSR) Field Descriptions................................................ 559
16-13. ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions............................................ 560
16-14. ESM Interrupt Offset Low Register (ESMIOFFLR) Field Descriptions............................................. 561
16-15. ESM Low-Time Counter Register (ESMLTCR) Field Descriptions................................................. 562
16-16. ESM Low-Time Counter Preload Register (ESMLTCPR) Field Descriptions..................................... 562
16-17. ESM Error Key Register (ESMEKR) Field Descriptions ............................................................. 563
16-18. ESM Status Shadow Register 2 (ESMSSR2) Field Descriptions .................................................. 563
16-19. ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) Field Descriptions........................... 564
16-20. ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) Field Descriptions ........................ 564
16-21. ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) Field Descriptions ................................... 565
16-22. ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4) Field Descriptions................................. 565
16-23. ESM Interrupt Level Set/Status Register 4 (ESMILSR4) Field Descriptions...................................... 566
16-24. ESM Interrupt Level Clear/Status Register 4 (ESMILCR4) Field Descriptions ................................... 566
16-25. ESM Status Register 4 (ESMSR4) Field Descriptions............................................................... 567
16-26. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) Field Descriptions........................... 568
16-27. ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) Field Descriptions ........................ 568
77
SPNU563–May 2014 List of Tables
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