Datasheet

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7-50. POM Flag Register (POMFLG) Field Descriptions ................................................................... 376
7-51. POM Region Start Address Register (POMPROGSTARTx) Field Descriptions.................................. 377
7-52. POM Overlay Region Start Address Register (POMOVLSTARTx) Field Descriptions.......................... 377
7-53. POM Region Size Register (POMREGSIZEx) Field Descriptions.................................................. 378
8-1. L2RAMW Error Types.................................................................................................... 382
8-2. L2RAMW Module Control and Status Registers...................................................................... 385
8-3. L2RAMW Module Control Register (RAMCTRL) Field Descriptions............................................... 385
8-4. L2RAMW Module Error Status Register (RAMERRSTATUS) Field Descriptions................................ 387
8-5. L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H) Field Descriptions............. 390
8-6. L2RAMW Diagnostic Vector Low Register (DIAG_DATA_VECTOR_L) Field Descriptions .................... 390
8-7. L2RAMW Diagnostic ECC Vector Register (DIAG_ECC) Field Descriptions..................................... 391
8-8. L2RAMW Module Test Mode Control Register (RAMTEST) Field Descriptions ................................. 392
8-9. L2RAMW RAM Address Decode Vector Test Register (RAMADDRDEC_VECT) Field Descriptions......... 393
8-10. L2RAMW Memory Initialization Domain Register (MEMINIT_DOMAIN) Field Descriptions.................... 394
8-11. L2RAMW Bank to Domain Mapping Register0 (BANK_DOMAIN_MAP0) Field Descriptions.................. 395
8-12. L2RAMW Bank to Domain Mapping Register1 (BANK_DOMAIN_MAP1) Field Descriptions.................. 396
9-1. PBIST Registers .......................................................................................................... 404
9-2. RAM Configuration Register (RAMT) Field Descriptions ............................................................ 405
9-3. Datalogger Register (DLR) Field Descriptions ........................................................................ 406
9-4. PBIST Activate/ROM Clock Enable Register (PACT) Field Descriptions ......................................... 407
9-5. PBIST ID Register Field Descriptions.................................................................................. 408
9-6. Override Register (OVER) Field Descriptions......................................................................... 409
9-7. Fail Status Fail Register 0 (FSRF0) Field Descriptions.............................................................. 410
9-8. Fail Status Fail Register 1 (FSRF1) Field Descriptions.............................................................. 410
9-9. Fail Status Count 0 Register (FSRC0) Field Descriptions........................................................... 411
9-10. Fail Status Count Register 1 (FSRC1) Field Descriptions........................................................... 411
9-11. Fail Status Address Register 0 (FSRA0) Field Descriptions ........................................................ 412
9-12. Fail Status Address Register 1 (FSRA1) Field Descriptions ........................................................ 412
9-13. Fail Status Data Register 0 (FSRDL0) Field Descriptions........................................................... 413
9-14. Fail Status Data Register 1 (FSRDL1) Field Descriptions........................................................... 413
9-15. ROM Mask Register (ROM) Field Descriptions....................................................................... 414
9-16. Algorithm Mask Register (ALGO) Field Descriptions ................................................................ 415
9-17. RAM Info Mask Lower Register (RINFOL) Field Descriptions...................................................... 416
9-18. RAM Info Mask Upper Register (RINFOU) Field Descriptions ..................................................... 417
10-1. STC Module Assignments ............................................................................................... 428
10-2. STC1 Segment 0 Test Coverage and Duration....................................................................... 433
10-3. Typical Execution Times for STC1 Segment 0 ....................................................................... 434
10-4. STC1 Segment 1 Test Coverage and Duration....................................................................... 435
10-5. Typical Execution Times for STC1 Segment 1 ....................................................................... 435
10-6. STC2 Test Coverage and Duration .................................................................................... 436
10-7. Typical Execution Times for STC2 ..................................................................................... 436
10-8. STC Control Registers ................................................................................................... 437
10-9. STC Global Control Register 0 (STCGCR0) Field Descriptions.................................................... 438
10-10. STC Global Control Register 1 (STCGCR1) Field Descriptions.................................................... 439
10-11. Self-Test Run Timeout Counter Preload Register (STCTPR) ...................................................... 439
10-12. STC Current ROM Address Register (STCCADDR1) Field Descriptions ......................................... 440
10-13. STC Current Interval Count Register (STCCICR) Field Descriptions.............................................. 440
10-14. Self-Test Global Status Register (STCGSTAT) Field Descriptions ................................................ 441
10-15. Self-Test Fail Status Register (STCFSTAT) Field Descriptions .................................................... 442
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SPNU563–May 2014 List of Tables
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