Datasheet

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List of Tables
2-1. Definition of Terms........................................................................................................ 112
2-2. Module Registers / Memories Memory Map .......................................................................... 119
2-3. Flash Memory Banks and Sectors...................................................................................... 127
2-4. EPC Registers Bit Mapping ............................................................................................. 130
2-5. PBIST Memory Grouping ................................................................................................ 131
2-6. PBIST Algorithm Mapping ............................................................................................... 133
2-7. Memory Initialization Select Mapping .................................................................................. 135
2-8. Causes of Resets......................................................................................................... 136
2-9. Clock Sources............................................................................................................. 139
2-10. Clock Domains ............................................................................................................ 140
2-11. Typical Low-Power Modes............................................................................................... 142
2-12. Clock Test Mode Options................................................................................................ 144
2-13. EXTCTL_Out_Port Register Field Descriptions ...................................................................... 145
2-14. DCC1 Counter 0 Clock Inputs .......................................................................................... 147
2-15. DCC1 Counter 1 Clock / Signal Inputs................................................................................. 147
2-16. DCC2 Counter 0 Clock Inputs .......................................................................................... 147
2-17. DCC2 Counter 1 Clock / Signal Inputs................................................................................. 147
2-18. Primary System Control Registers ..................................................................................... 148
2-19. SYS Pin Control Register 1 (SYSPC1) Field Descriptions.......................................................... 150
2-20. SYS Pin Control Register 2 (SYSPC2) Field Descriptions.......................................................... 150
2-21. SYS Pin Control Register 3 (SYSPC3) Field Descriptions.......................................................... 151
2-22. SYS Pin Control Register 4 (SYSPC4) Field Descriptions.......................................................... 151
2-23. SYS Pin Control Register 5 (SYSPC5) Field Descriptions.......................................................... 152
2-24. SYS Pin Control Register 6 (SYSPC6) Field Descriptions.......................................................... 152
2-25. SYS Pin Control Register 7 (SYSPC7) Field Descriptions.......................................................... 153
2-26. SYS Pin Control Register 8 (SYSPC8) Field Descriptions.......................................................... 153
2-27. SYS Pin Control Register 9 (SYSPC9) Field Descriptions.......................................................... 154
2-28. Clock Source Disable Register (CSDIS) Field Descriptions ........................................................ 155
2-29. Clock Sources Table ..................................................................................................... 155
2-30. Clock Source Disable Set Register (CSDISSET) Field Descriptions .............................................. 156
2-31. Clock Source Disable Clear Register (CSDISCLR) Field Descriptions............................................ 157
2-32. Clock Domain Disable Register (CDDIS) Field Descriptions ....................................................... 158
2-33. Clock Domain Disable Set Register (CDDISSET) Field Descriptions ............................................. 159
2-34. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions........................................... 161
2-35. GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) Field Descriptions ............................. 163
2-36. Peripheral Asynchronous Clock Source Register (VCLKASRC) Field Descriptions............................. 164
2-37. RTI Clock Source Register (RCLKSRC) Field Descriptions ........................................................ 165
2-38. Clock Source Valid Register (CSVSTAT) Field Descriptions ....................................................... 166
2-39. Memory Self-Test Global Control Register (MSTGCR) Field Descriptions ....................................... 167
2-40. Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions ...................... 168
2-41. MBIST Controller/Memory Initialization Enable Register (MSINENA) Field Descriptions....................... 169
2-42. MSTC Global Status Register (MSTCGSTAT) Field Descriptions ................................................. 170
2-43. Memory Hardware Initialization Status Register (MINISTAT) Field Descriptions ................................ 171
2-44. PLL Control Register 1 (PLLCTL1) Field Descriptions .............................................................. 172
2-45. PLL Control Register 2 (PLLCTL2) Field Descriptions .............................................................. 173
2-46. SYS Pin Control Register 10 (SYSPC10) Field Descriptions....................................................... 174
2-47. Die Identification Register, Lower Word (DIEIDL) Field Descriptions.............................................. 175
70
List of Tables SPNU563–May 2014
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