Datasheet

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36-26. DMM Pin Control 4 (DMMPC4) [offset = 7Ch] ...................................................................... 2079
36-27. DMM Pin Control 5 (DMMPC5) [offset = 80h]....................................................................... 2081
36-28. DMM Pin Control 6 (DMMPC6) [offset = 84h]....................................................................... 2082
36-29. DMM Pin Control 7 (DMMPC7) [offset = 88h]....................................................................... 2084
36-30. DMM Pin Control 8 (DMMPC8) [offset = 8Ch] ...................................................................... 2085
37-1. RAM Trace Port Module Block Diagram ............................................................................. 2089
37-2. Packet Format Trace Mode for RAM Locations..................................................................... 2090
37-3. Packet Format Trace Mode for Peripheral Locations .............................................................. 2090
37-4. Packet Format in Direct Data Mode .................................................................................. 2092
37-5. Example for Trace Region Setup ..................................................................................... 2093
37-6. FIFO Overflow Handling................................................................................................ 2094
37-7. RTP Packet Transfer with Sync Signal............................................................................... 2095
37-8. Packet Format in Trace Mode ......................................................................................... 2095
37-9. RTP Global Control Register (RTPGLBCTRL) (offset = 00h) ..................................................... 2097
37-10. RTP Trace Enable Register (RTPTRENA) (offset = 04h).......................................................... 2100
37-11. RTP Global Status Register (RTPGSR) (offset = 08h)............................................................. 2102
37-12. RTP RAM 1 Trace Region Registers (RTPRAM1REGn) (offset = 0Ch and 10h) .............................. 2104
37-13. RTP RAM 2 Trace Region Registers (RTPRAM2REGn) (offset = 14h and 18h)............................... 2105
37-14. RTP RAM 3 Trace Region Registers (RTPRAM3REGn) (offset = 1Ch and 20h) .............................. 2106
37-15. RTP Peripheral Trace Region Registers (RTPPERREGn) (offset = 24h and 28h)............................. 2108
37-16. RTP Direct Data Mode Write Register (RTPDDMW) (offset = 2Ch) ............................................. 2109
37-17. RTP Pin Control 0 Register (RTPPC0) (offset = 34h).............................................................. 2110
37-18. RTP Pin Control 1 Register (RTPPC1) (offset = 38h).............................................................. 2111
37-19. RTP Pin Control 2 Register (RTPPC2) (offset = 3Ch) ............................................................. 2112
37-20. RTP Pin Control 3 Register (RTPPC3) (offset = 40h).............................................................. 2113
37-21. RTP Pin Control 4 Register (RTPPC4) (offset = 44h).............................................................. 2114
37-22. RTP Pin Control 5 Register (RTPPC5) (offset = 48h).............................................................. 2115
37-23. RTP Pin Control 6 Register (RTPPC6) (offset = 4Ch) ............................................................. 2116
37-24. RTP Pin Control 7 Register (RTPPC7) (offset = 50h).............................................................. 2118
37-25. RTP Pin Control 8 Register (RTPPC8) (offset = 54h).............................................................. 2119
38-1. eFuse Self Test Flow Chart............................................................................................ 2123
38-2. EFC Boundary Control Register (EFCBOUND) [offset = 1Ch].................................................... 2124
38-3. EFC Pins Register (EFCPINS) [offset = 2Ch] ...................................................................... 2126
38-4. EFC Error Status Register (EFCERRSTAT) [offset = 3Ch]........................................................ 2127
38-5. EFC Self Test Cycles Register (EFCSTCY) [offset = 48h] ........................................................ 2127
38-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch] ....................................................... 2128
69
SPNU563–May 2014 List of Figures
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