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35-77. Dead-Band Generator Rising Edge Delay Register (DBRED) [offset = 22h].................................... 2017
35-78. Trip Zone Digital Compare Event Select Register (TZDCSEL) [offset = 24h ].................................. 2018
35-79. Trip-Zone Select Register (TZSEL) [offset = 26h] .................................................................. 2019
35-80. Trip-Zone Enable Interrupt Register (TZEINT) [offset = 28h]...................................................... 2021
35-81. Trip-Zone Control Register (TZCTL) [offset = 2Ah]................................................................. 2022
35-82. Trip-Zone Clear Register (TZCLR) [offset = 2Ch]................................................................... 2023
35-83. Trip-Zone Flag Register (TZFLG) [offset = 2Eh] .................................................................... 2024
35-84. Trip-Zone Force Register (TZFRC) [offset = 32h] .................................................................. 2025
35-85. Event-Trigger Selection Register (ETSEL) [offset = 30h] .......................................................... 2026
35-86. Event-Trigger Flag Register (ETFLG) [offset = 34h]................................................................ 2027
35-87. Event-Trigger Prescale Register (ETPS) [offset = 36h] ............................................................ 2028
35-88. Event-Trigger Force Register (ETFRC) [offset = 38h].............................................................. 2030
35-89. Event-Trigger Clear Register (ETCLR) [offset = 3Ah] .............................................................. 2031
35-90. PWM-Chopper Control Register (PCCTL) [offset = 3Eh ........................................................... 2032
35-91. Digital Compare A Control Register (DCACTL) [offset = 60h] .................................................... 2034
35-92. Digital Compare Trip Select (DCTRIPSEL) [offset = 62h] ......................................................... 2035
35-93. Digital Compare Filter Control Register (DCFCTL) [offset = 64h] ................................................ 2036
35-94. Digital Compare B Control Register (DCBCTL) [offset = 66h] .................................................... 2037
35-95. Digital Compare Filter Offset Register (DCFOFFSET) [offset = 68h] ............................................ 2038
35-96. Digital Compare Capture Control Register (DCCAPCTL) [offset = 6Ah]......................................... 2038
35-97. Digital Compare Filter Window Register (DCFWINDOW) [offset = 6Ch] ........................................ 2039
35-98. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) [offset = 6Eh] ............................ 2039
35-99. Digital Compare Counter Capture Register (DCCAP) [offset = 70h] ............................................. 2040
35-100. Digital Compare Filter Window Counter Register (DCFWINDOWCNT) [offset = 72h] ....................... 2040
36-1. DMM Block Diagram.................................................................................................... 2042
36-2. Trace Mode Packet Format............................................................................................ 2044
36-3. Direct Data Mode Packet Format ..................................................................................... 2044
36-4. Packet Sync Signal Example .......................................................................................... 2046
36-5. Example Single Packet Transmission ................................................................................ 2046
36-6. Interrupt Structure ....................................................................................................... 2047
36-7. DMM Global Control Register (DMMGLBCTRL) [offset = 00h] ................................................... 2049
36-8. DMM Interrupt Set Register (DMMINTSET) [offset = 04h]......................................................... 2051
36-9. DMM Interrupt Clear Register (DMMINTCLR) [offset = 08h] ...................................................... 2055
36-10. DMM Interrupt Level Register (DMMINTLVL) [offset = 0Ch] ...................................................... 2060
36-11. DMM Interrupt Flag Register (DMMINTFLG) [offset = 10h] ....................................................... 2062
36-12. DMM Interrupt Offset 1 Register (DMMOFF1) [offset = 14h]...................................................... 2066
36-13. DMM Interrupt Offset 2 Register (DMMOFF2) [offset = 18h]...................................................... 2067
36-14. DMM Direct Data Mode Destination Register (DMMDDMDEST) [offset = 1Ch]................................ 2068
36-15. DMM Direct Data Mode Blocksize Register (DMMDDMBL) [offset = 20h] ...................................... 2068
36-16. DMM Direct Data Mode Pointer Register (DMMDDMPT) [offset = 24h] ......................................... 2069
36-17. DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) [offset = 28h] ................................ 2069
36-18. DMM Destination x Region 1 (DMMDESTxREG1) [offset = 2Ch, 3Ch, 4Ch, 5Ch]............................. 2070
36-19. DMM Destination x Blocksize 1 (DMMDESTxBL1) [offset = 30h, 40h, 50h, 60h] .............................. 2071
36-20. DMM Destination x Region 2 (DMMDESTxREG2) [offset = 34h, 44h, 54h, 64h] .............................. 2072
36-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) [offset = 38h, 48h, 58h, 68h] .............................. 2073
36-22. DMM Pin Control 0 (DMMPC0) [offset = 6Ch] ...................................................................... 2074
36-23. DMM Pin Control 1 (DMMPC1) [offset = 70h]....................................................................... 2075
36-24. DMM Pin Control 2 (DMMPC2) [offset = 74h]....................................................................... 2077
36-25. DMM Pin Control 3 (DMMPC3) [offset = 78h]....................................................................... 2078
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List of Figures SPNU563–May 2014
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