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35-29. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 1964
35-30. PWM-Chopper Submodule ............................................................................................ 1966
35-31. PWM-Chopper Submodule Operational Details..................................................................... 1967
35-32. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only............................... 1967
35-33. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses...... 1968
35-34. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses..................................................................................................................... 1969
35-35. Trip-Zone Submodule................................................................................................... 1970
35-36. Trip-Zone Submodule Mode Control Logic .......................................................................... 1974
35-37. Trip-Zone Submodule Interrupt Logic................................................................................. 1975
35-38. Event-Trigger Submodule .............................................................................................. 1976
35-39. Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion....................................... 1977
35-40. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 1978
35-41. Event-Trigger Interrupt Generator..................................................................................... 1980
35-42. Event-Trigger SOCA Pulse Generator ............................................................................... 1980
35-43. Event-Trigger SOCB Pulse Generator ............................................................................... 1981
35-44. Digital-Compare Submodule High-Level Block Diagram........................................................... 1981
35-45. DCAEVT1 Event Triggering............................................................................................ 1984
35-46. DCAEVT2 Event Triggering............................................................................................ 1984
35-47. DCBEVT1 Event Triggering............................................................................................ 1985
35-48. DCBEVT2 Event Triggering............................................................................................ 1985
35-49. Event Filtering ........................................................................................................... 1986
35-50. Blanking Window Timing Diagram .................................................................................... 1987
35-51. Simplified ePWM Module............................................................................................... 1988
35-52. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ..................................... 1989
35-53. Control of Four Buck Stages. Here F
PWM1
≠ F
PWM2
≠ F
PWM3
≠ F
PWM4
.................................................. 1990
35-54. Buck Waveforms for (Note: Only three bucks shown here) ....................................................... 1991
35-55. Control of Four Buck Stages. (Note: F
PWM2
= N x F
PWM1
)............................................................ 1993
35-56. Buck Waveforms for (Note: F
PWM2
= F
PWM1)
)........................................................................... 1994
35-57. Control of Two Half-H Bridge Stages (F
PWM2
= N x F
PWM1
).......................................................... 1996
35-58. Half-H Bridge Waveforms for (Note: Here F
PWM2
= F
PWM1
).......................................................... 1997
35-59. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................. 1999
35-60. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ..................................................... 2000
35-61. Configuring Two PWM Modules for Phase Control................................................................. 2001
35-62. Timing Waveforms Associated With Phase Control Between 2 Modules ....................................... 2002
35-63. Time-Base Status Register (TBSTS) [offset = 00h]................................................................. 2004
35-64. Time-Base Control Register (TBCTL) [offset = 02h]................................................................ 2005
35-65. Time-Base Phase Register (TBPHS) [offset = 04h] ................................................................ 2007
35-66. Time-Base Period Register (TBPRD) [offset = 08h] ................................................................ 2007
35-67. Time-Base Counter Register (TBCTR) [offset = 0Ah ] ............................................................. 2007
35-68. Counter-Compare Control Register (CMPCTL) [offset = 0Ch] .................................................... 2008
35-69. Counter-Compare A Register (CMPA) [offset = 10h]............................................................... 2009
35-70. Counter-Compare B Register (CMPB) [offset = 16h]............................................................... 2010
35-71. Action-Qualifier Output A Control Register (AQCTLA) [offset = 14h] ............................................ 2011
35-72. Action-Qualifier Software Force Register (AQSFRC) [offset = 18h].............................................. 2012
35-73. Action-Qualifier Output B Control Register (AQCTLB) [offset = 1Ah] ............................................ 2013
35-74. Action-Qualifier Continuous Software Force Register (AQCSFRC) [offset = 1Eh] ............................. 2014
35-75. Dead-Band Generator Control Register (DBCTL) [offset = 1Ch] ................................................. 2015
35-76. Dead-Band Generator Falling Edge Delay Register (DBFED) [offset = 20h] ................................... 2017
67
SPNU563–May 2014 List of Figures
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