Datasheet

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32-44. Receive Teardown Register (RXTEARDOWN) (offset = 18h) .................................................... 1818
32-45. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) (offset = 80h) ............................ 1819
32-46. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) (offset = 84h) .......................... 1820
32-47. Transmit Interrupt Mask Set Register (TXINTMASKSET) (offset = 88h) ........................................ 1821
32-48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) (offset = 8Ch).................................. 1822
32-49. MAC Input Vector Register (MACINVECTOR) (offset = 90h) ..................................................... 1823
32-50. MAC End Of Interrupt Vector Register (MACEOIVECTOR) (offset = 94h)...................................... 1824
32-51. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) (offset = A0h) ............................ 1825
32-52. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) (offset = A4h)........................... 1826
32-53. Receive Interrupt Mask Set Register (RXINTMASKSET) (offset = A8h) ........................................ 1827
32-54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) (offset = ACh).................................. 1828
32-55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) (offset = B0h).............................. 1829
32-56. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) (offset = B4h) ............................ 1829
32-57. MAC Interrupt Mask Set Register (MACINTMASKSET) (offset = B8h).......................................... 1830
32-58. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) (offset = BCh) ................................... 1830
32-59. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) (offset = 100h) .. 1831
32-60. Receive Unicast Enable Set Register (RXUNICASTSET) (offset = 104h) ...................................... 1833
32-61. Receive Unicast Clear Register (RXUNICASTCLEAR) (offset = 108h).......................................... 1834
32-62. Receive Maximum Length Register (RXMAXLEN) (offset = 10Ch) .............................................. 1834
32-63. Receive Buffer Offset Register (RXBUFFEROFFSET) (offset = 110h) .......................................... 1835
32-64. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) (offset = 114h).......... 1835
32-65. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) (offset = 120h-13Ch).......... 1836
32-66. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) (offset = 140h-15Ch) ................. 1836
32-67. MAC Control Register (MACCONTROL) (offset = 160h) .......................................................... 1837
32-68. MAC Status Register (MACSTATUS) (offset = 164h).............................................................. 1839
32-69. Emulation Control Register (EMCONTROL) (offset = 168h) ...................................................... 1841
32-70. FIFO Control Register (FIFOCONTROL) (offset = 16Ch) ......................................................... 1841
32-71. MAC Configuration Register (MACCONFIG) (offset = 170h)...................................................... 1842
32-72. Soft Reset Register (SOFTRESET) (offset = 174h) ................................................................ 1842
32-73. MAC Source Address Low Bytes Register (MACSRCADDRLO) (offset = 1D0h) .............................. 1843
32-74. MAC Source Address High Bytes Register (MACSRCADDRHI) (offset = 1D4h) .............................. 1843
32-75. MAC Hash Address Register 1 (MACHASH1) (offset = 1D8h) ................................................... 1844
32-76. MAC Hash Address Register 2 (MACHASH2) (offset = 1DCh)................................................... 1844
32-77. Back Off Random Number Generator Test Register (BOFFTEST) (offset = 1E0h)............................ 1845
32-78. Transmit Pacing Algorithm Test Register (TPACETEST) (offset = 1E4h)....................................... 1845
32-79. Receive Pause Timer Register (RXPAUSE) (offset = 1E8h)...................................................... 1846
32-80. Transmit Pause Timer Register (TXPAUSE) (offset = 1ECh)..................................................... 1846
32-81. MAC Address Low Bytes Register (MACADDRLO) (offset = 500h).............................................. 1847
32-82. MAC Address High Bytes Register (MACADDRHI) (offset = 504h) .............................................. 1848
32-83. MAC Index Register (MACINDEX) (offset = 508h) ................................................................. 1848
32-84. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) (offset = 600h-61Ch)............... 1849
32-85. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) (offset = 620h-63Ch) ............... 1849
32-86. Transmit Channel n Completion Pointer Register (TXnCP) (offset = 640h-65Ch) ............................. 1850
32-87. Receive Channel n Completion Pointer Register (RXnCP) (offset = 660h-67Ch).............................. 1850
32-88. Statistics Register ....................................................................................................... 1851
33-1. Capture and APWM Modes of Operation ............................................................................ 1862
33-2. Capture Function Diagram ............................................................................................. 1863
33-3. Event Prescale Control ................................................................................................. 1864
33-4. Prescale Function Waveforms......................................................................................... 1864
64
List of Figures SPNU563–May 2014
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