Datasheet

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31-35. I2C Data Clear Register (I2CDCLR) [offset = 5Ch]................................................................. 1736
31-36. I2C Pin Open Drain Register (I2CPDR) [offset = 60h] ............................................................. 1736
31-37. I2C Pull Disable Register (I2CPDIS) [offset = 64h]................................................................. 1737
31-38. I2C Pull Select Register (I2CPSEL) [offset = 68h].................................................................. 1737
31-39. I2C Pins Slew Rate Select Register (I2CSRS) [offset = 6Ch]..................................................... 1738
31-40. Difference between Normal Operation and Backward Compatibility Mode...................................... 1739
32-1. EMAC and MDIO Block Diagram ..................................................................................... 1742
32-2. Ethernet Configuration—MII Connections ........................................................................... 1744
32-3. Ethernet Configuration—RMII Connections.......................................................................... 1746
32-4. Ethernet Frame Format................................................................................................. 1748
32-5. Basic Descriptor Format................................................................................................ 1749
32-6. Typical Descriptor Linked List ......................................................................................... 1750
32-7. Transmit Buffer Descriptor Format.................................................................................... 1753
32-8. Receive Buffer Descriptor Format..................................................................................... 1756
32-9. EMAC Control Module Block Diagram ............................................................................... 1760
32-10. MDIO Module Block Diagram.......................................................................................... 1761
32-11. EMAC Module Block Diagram......................................................................................... 1766
32-12. EMAC Control Module Revision ID Register (REVID) (offset = 00h)............................................. 1788
32-13. EMAC Control Module Software Reset Register (SOFTRESET) (offset = 04h) ................................ 1788
32-14. EMAC Control Module Interrupt Control Register (INTCONTROL) (offset = 0Ch) ............................. 1789
32-15. EMAC Control Module Receive Threshold Interrupt Enable Register (C0RXTHRESHEN) (offset = 10h) .. 1790
32-16. EMAC Control Module Receive Interrupt Enable Register (C0RXEN) (offset = 14h) .......................... 1791
32-17. EMAC Control Module Transmit Interrupt Enable Register (C0TXEN) (offset = 18h) ......................... 1792
32-18. EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN) (offset = 1Ch) ............... 1793
32-19. EMAC Control Module Receive Threshold Interrupt Status Register (C0RXTHRESHSTAT) (offset = 40h) 1794
32-20. EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) (offset = 44h) ....................... 1795
32-21. EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) (offset = 48h) ....................... 1796
32-22. EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT) (offset = 4Ch)............. 1797
32-23. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX) (offset = 70h)............ 1798
32-24. EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) (offset = 74h) ........... 1799
32-25. MDIO Revision ID Register (REVID) (offset = 00h) ................................................................ 1800
32-26. MDIO Control Register (CONTROL) (offset = 04h)................................................................. 1801
32-27. PHY Acknowledge Status Register (ALIVE) (offset = 08h)........................................................ 1802
32-28. PHY Link Status Register (LINK) (offset = 0Ch) .................................................................... 1802
32-29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) (offset = 10h) .................... 1803
32-30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) (offset = 14h) .................. 1804
32-31. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) (offset = 20h)........... 1805
32-32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) (offset = 24h) ......... 1806
32-33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) (offset = 28h)........ 1807
32-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) (offset = 2Ch) . 1808
32-35. MDIO User Access Register 0 (USERACCESS0) (offset = 80h) ................................................. 1809
32-36. MDIO User PHY Select Register 0 (USERPHYSEL0) (offset = 84h) ............................................ 1810
32-37. MDIO User Access Register 1 (USERACCESS1) (offset = 88h) ................................................. 1811
32-38. MDIO User PHY Select Register 1 (USERPHYSEL1) (offset = 8Ch)............................................ 1812
32-39. Transmit Revision ID Register (TXREVID) (offset = 00h).......................................................... 1816
32-40. Transmit Control Register (TXCONTROL) (offset = 04h).......................................................... 1816
32-41. Transmit Teardown Register (TXTEARDOWN) (offset = 08h) .................................................... 1817
32-42. Receive Revision ID Register (RXREVID) (offset = 10h) .......................................................... 1817
32-43. Receive Control Register (RXCONTROL) (offset = 14h) .......................................................... 1818
63
SPNU563–May 2014 List of Figures
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