Datasheet

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30-18. Baud Rate Selection Register (BRS) [offset = 2Ch] ................................................................ 1688
30-19. Receiver Emulation Data Buffer (SCIED) [offset = 30h] ........................................................... 1689
30-20. Receiver Data Buffer (SCIRD) [offset = 34h] ........................................................................ 1689
30-21. Transmit Data Buffer Register (SCITD) [offset = 38h].............................................................. 1690
30-22. SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch] ......................................................... 1690
30-23. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h]........................................................... 1691
30-24. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h] .......................................................... 1692
30-25. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h]........................................................... 1693
30-26. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch] ......................................................... 1694
30-27. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h]........................................................... 1695
30-28. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h] .......................................................... 1696
30-29. SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h]........................................................... 1697
30-30. SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch] ......................................................... 1697
30-31. Input/Output Error Enable Register (IODFTCTRL) [offset = 90h]................................................. 1698
30-32. GPIO Functionality ...................................................................................................... 1700
31-1. Multiple I2C Modules Connection Diagram .......................................................................... 1703
31-2. Simple I2C Block Diagram ............................................................................................. 1705
31-3. Clocking Diagram for the I2C Module ................................................................................ 1706
31-4. Bit Transfer on the I2C Bus ............................................................................................ 1707
31-5. I2C Module START and STOP Conditions .......................................................................... 1708
31-6. I2C Module Data Transfer.............................................................................................. 1708
31-7. I2C Module 7-Bit Addressing Format ................................................................................. 1709
31-8. I2C Module 10-bit Addressing Format................................................................................ 1709
31-9. I2C Module 7-Bit Addressing Format with Repeated START ..................................................... 1709
31-10. I2C Module in Free Data Format...................................................................................... 1710
31-11. Arbitration Procedure Between Two Master Transmitters ......................................................... 1713
31-12. Synchronization of Two I2C Clock Generators During Arbitration................................................ 1714
31-13. I2C Own Address Manager Register (I2COAR) [offset = 00] ..................................................... 1719
31-14. I2C Interrupt Mask Register (I2CIMR) [offset = 04h] ............................................................... 1720
31-15. I2C Status Register (I2CSR) [offset = 08h] .......................................................................... 1721
31-16. I2C Clock Divider Low Register (I2CCKL) [offset = 0Ch] .......................................................... 1724
31-17. I2C Clock Control High Register (I2CCKH) [offset = 10h] ......................................................... 1724
31-18. I2C Data Count Register (I2CCNT) [offset = 14h] .................................................................. 1725
31-19. I2C Data Receive Register (I2CDRR) [offset = 18h] ............................................................... 1725
31-20. I2C Slave Address Register (I2CSAR) [offset = 1Ch] .............................................................. 1726
31-21. I2C Data Transmit Register (I2CDXR) [offset = 20h]............................................................... 1726
31-22. I2C Mode Register (I2CMDR) [offset = 24h]......................................................................... 1727
31-23. Typical Timing Diagram of Repeat Mode ............................................................................ 1729
31-24. I2C Interrupt Vector Register (I2CIVR) [offset = 28h] .............................................................. 1730
31-25. I2C Extended Mode Register (I2CEMDR) [offset = 2Ch] .......................................................... 1731
31-26. I2C Prescale Register (I2CPSC) [offset = 30h] ..................................................................... 1731
31-27. I2C Peripheral ID Register 1 (I2CPID1) [offset = 34h] ............................................................. 1732
31-28. I2C Peripheral ID Register 2 (I2CPID2) [offset = 38h] ............................................................. 1732
31-29. I2C DMA Control Register (I2CDMACR) [offset = 3Ch]............................................................ 1733
31-30. I2C Pin Function Register (I2CPFNC) [offset = 48h] ............................................................... 1733
31-31. I2C Pin Direction Register (I2CPDIR) [offset = 4Ch] ............................................................... 1734
31-32. I2C Data Input Register (I2CDIN) [offset = 50h] .................................................................... 1734
31-33. I2C Data Output Register (I2CDOUT) [offset 0x54] ................................................................ 1735
31-34. I2C Data Set Register (I2CDSET) [offset = 58h].................................................................... 1735
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List of Figures SPNU563–May 2014
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