Datasheet

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28-82. ECC Diagnostic Status Register (ECCDIAG_STAT) [offset = 144h] ............................................. 1540
28-83. Single Bit Error Address Register - RXRAM (SBERRADDR1) [offset = 148h].................................. 1541
28-84. Single Bit Error Address Register - TXRAM (SBERRADDR0) [offset = 14Ch] ................................. 1542
28-85. Multi-buffer RAM Configuration When Parity Check is Supported................................................ 1543
28-86. Multi-buffer RAM Configuration When ECC Check is Supported................................................. 1543
28-87. Multi-buffer RAM Transmit Data Register [offset = Base + 000-1FFh]........................................... 1545
28-88. Multi-buffer RAM Receive Buffer Register [offset = RAM Base + 200-3FFh] ................................... 1547
28-89. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Disabled or the Feature is Not Implemented ........................................................................ 1550
28-90. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Enabled................................................................................................................... 1551
28-91. Example of Memory-Mapped Parity Locations During Test Mode................................................ 1552
28-92. Example of ECC Bit Locations During Test Mode .................................................................. 1553
28-93. SPI/MibSPI Pins During Master Mode 3-Pin Configuration........................................................ 1554
28-94. SPI/MibSPI Pins During Master Mode 4-Pin with SPISCS Configuation ........................................ 1554
28-95. SPI/MibSPI Pins During Master Mode in 4-Pin with SPIENA Configuration .................................... 1555
28-96. SPI/MibSPI Pins During Master/Slave Mode with 5-Pin Configuration .......................................... 1555
28-97. SPI/MibSPI Pins During Slave Mode 3-Pin Configuration ......................................................... 1556
28-98. SPI/MibSPI Pins During Slave Mode in 4-Pin with SPIENA Configuration...................................... 1556
28-99. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single Slave)..................................... 1556
28-100. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single/Multi-Slave)............................. 1556
29-1. SCI Block Diagram...................................................................................................... 1562
29-2. SCI/LIN Block Diagram................................................................................................. 1563
29-3. Typical SCI Data Frame Formats ..................................................................................... 1564
29-4. Asynchronous Communication Bit Timing ........................................................................... 1565
29-5. Superfractional Divider Example ...................................................................................... 1567
29-6. Idle-Line Multiprocessor Communication Format ................................................................... 1569
29-7. Address-Bit Multiprocessor Communication Format................................................................ 1569
29-8. Receive Buffers.......................................................................................................... 1570
29-9. Transmit Buffers ......................................................................................................... 1571
29-10. General Interrupt Scheme.............................................................................................. 1572
29-11. Interrupt Generation for Given Flags ................................................................................. 1573
29-12. LIN Protocol Message Frame Format: Master Header and Slave Response ................................... 1580
29-13. Header 3 Fields: Synch Break, Synch, and ID ...................................................................... 1580
29-14. Response Format of LIN Message Frame........................................................................... 1581
29-15. Message Header in Terms of T
bit
...................................................................................... 1584
29-16. ID Field ................................................................................................................... 1584
29-17. Measurements for Synchronization ................................................................................... 1586
29-18. Synchronization Validation Process and Baud Rate Adjustment ................................................. 1587
29-19. Optional Embedded Checksum in Response for Extended Frames ............................................. 1588
29-20. Checksum Compare and Send for Extended Frames.............................................................. 1589
29-21. TXRX Error Detector.................................................................................................... 1591
29-22. Classic Checksum Generation at Transmitting Node .............................................................. 1592
29-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node ................................................. 1592
29-24. ID Reception, Filtering and Validation ................................................................................ 1594
29-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence .............................................. 1596
29-26. Wakeup Signal Generation ............................................................................................ 1600
29-27. GPIO Functionality ...................................................................................................... 1602
29-28. SCI Global Control Register 0 (SCIGCR0) (offset = 00) ........................................................... 1605
60
List of Figures SPNU563–May 2014
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