Datasheet

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28-36. SPI Flag Register (SPIFLG) [offset = 10h] .......................................................................... 1483
28-37. SPI Pin Control Register 0 (SPIPC0) [offset = 14h] ................................................................ 1486
28-38. SPI Pin Control Register 1 (SPIPC1) [offset = 18h] ............................................................... 1487
28-39. SPI Pin Control Register 2 (SPIPC2) [offset = 1Ch]................................................................ 1489
28-40. SPI Pin Control Register 3 (SPIPC3) [offset = 20h] ............................................................... 1490
28-41. SPI Pin Control Register 4 (SPIPC4) [offset = 24h] ............................................................... 1491
28-42. SPI Pin Control Register 5 (SPIPC5) [offset = 28h] ............................................................... 1493
28-43. SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch] ............................................................... 1494
28-44. SPI Pin Control Register 7 (SPIPC7) [offset = 30h] ............................................................... 1496
28-45. SPI Pin Control Register 8 (SPIPC8) [offset = 34h] ............................................................... 1497
28-46. SPI Transmit Data Register 0 (SPIDAT0) [offset = 38h] ........................................................... 1498
28-47. SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch]........................................................... 1499
28-48. SPI Receive Buffer Register (SPIBUF) [offset = 40h] .............................................................. 1500
28-49. SPI Emulation Register (SPIEMU) [offset = 44h] ................................................................... 1502
28-50. SPI Delay Register (SPIDELAY) [offset = 48h] ..................................................................... 1502
28-51. Example: t
C2TDELAY
= 8 VCLK Cycles................................................................................... 1504
28-52. Example: t
T2CDELAY
= 4 VCLK Cycles................................................................................... 1504
28-53. Transmit-Data-Finished-to-ENA-Inactive-Timeout .................................................................. 1504
28-54. Chip-Select-Active-to-ENA-Signal-Active-Timeout.................................................................. 1504
28-55. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch] ........................................................ 1505
28-56. SPI Data Format Registers (SPIFMTn) [offset = 5Ch-50h]........................................................ 1506
28-57. Interrupt Vector 0 (NTVECT0) [offset = 60h] ........................................................................ 1508
28-58. Interrupt Vector 1 (INTVECT1) [offset = 64h]........................................................................ 1509
28-59. Parallel/Modulo Mode Control Register (SPIPMCTRL) [offset = 6Ch] ........................................... 1510
28-60. Multi-buffer Mode Enable Register (MIBSPIE) [offset = 70h]...................................................... 1513
28-61. TG Interrupt Enable Set Register (TGITENST) [offset = 74h]..................................................... 1514
28-62. TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h].................................................. 1515
28-63. Transfer Group Interrupt Level Set Register (TGITLVST) [offset = 7Ch] ........................................ 1516
28-64. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h]...................................... 1517
28-65. Transfer Group Interrupt Flag Register (TGINTFLAG) [offset = 84h] ............................................ 1518
28-66. Tick Counter Operation................................................................................................. 1519
28-67. Tick Count Register (TICKCNT) [offset = 90h] ...................................................................... 1519
28-68. Last TG End Pointer (LTGPEND) [offset = 94h] .................................................................... 1520
28-69. MibSPI TG Control Registers (TGxCTRL) [offsets = 98h-D4h] ................................................... 1521
28-70. DMA Channel Control Register (DMAxCTRL) [offset = D8h-F4h] ................................................ 1524
28-71. DMAxCOUNT Register (ICOUNT) [offset = F8h-114h] ............................................................ 1526
28-72. DMA Large Count Register (DMACNTLEN) [offset = 118h]....................................................... 1527
28-73. Parity/ECC Control Register (PAR_ECC_CTRL) [offset = 120]................................................... 1528
28-74. Parity/ECC Status Register (PAR_ECC_STAT) [offset = 124].................................................... 1529
28-75. Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1) [offset =
128h] ...................................................................................................................... 1530
28-76. Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) [offset =
12Ch]...................................................................................................................... 1532
28-77. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h]........................... 1533
28-78. I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h]........................................... 1534
28-79. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) [offset =
138h] ...................................................................................................................... 1536
28-80. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) [offset =
13Ch]...................................................................................................................... 1538
28-81. ECC Diagnostic Control Register (ECCDIAG_CTRL) [offset = 140h]............................................ 1539
59
SPNU563–May 2014 List of Figures
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