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26-160. FIFO Rejection Filter Mask Register (FRFM) [offset_CC = 308h]............................................... 1332
26-161. FIFO Critical Level Register (FCL) [offset_CC = 30Ch] .......................................................... 1332
26-162. Message Handler Status (MHDS) [offset_CC = 310h]............................................................ 1333
26-163. Last Dynamic Transmit Slot (LDTS) [offset_CC = 314h] ......................................................... 1334
26-164. FIFO Status Register (FSR) [offset_CC = 318h] .................................................................. 1335
26-165. Message Handler Constraints Flags (MHDF) [offset_CC = 31Ch] .............................................. 1336
26-166. Transmission Request Register 4 (TXRQ4) [offset_CC = 32Ch]................................................ 1338
26-167. Transmission Request Register 3 (TXRQ3) [offset_CC = 328h] ................................................ 1338
26-168. Transmission Request Register 2 (TXRQ2) [offset_CC = 324h] ................................................ 1338
26-169. Transmission Request Register 1 (TXRQ1) [offset_CC = 320h] ................................................ 1338
26-170. New Data Register 4 (NDAT4) [offset_CC = 33Ch] ............................................................... 1339
26-171. New Data Register 3 (NDAT3) [offset_CC = 338h] ............................................................... 1339
26-172. New Data Register 2 (NDAT2) [offset_CC = 334h] ............................................................... 1339
26-173. New Data Register 1 (NDAT1) [offset_CC = 330h] ............................................................... 1339
26-174. Message Buffer Status Changed Register 4 (MBSC4) [offset_CC = 34Ch] ................................... 1341
26-175. Message Buffer Status Changed Register 3 (MBSC3) [offset_CC = 348h].................................... 1341
26-176. Message Buffer Status Changed Register 2 (MBSC2) [offset_CC = 344h].................................... 1341
26-177. Message Buffer Status Changed Register 1 (MBSC1) [offset_CC = 340h].................................... 1341
26-178. Core Release Register (CREL) [offset_CC = 3F0h]............................................................... 1342
26-179. Endian Register (ENDN) [offset_CC = 3F4h] ...................................................................... 1342
26-180. Write Data Section Registers (WRDSn) [offset_CC = 400h-4FCh] ............................................. 1343
26-181. Write Header Section Register 1 (WRHS1) [offset_CC = 500h]................................................. 1344
26-182. Write Header Section Register 2 (WRHS2) [offset_CC = 504h]................................................. 1345
26-183. Write Header Section Register 3 (WRHS3) [offset_CC = 508h]................................................. 1346
26-184. Input Buffer Command Mask Register (IBCM) [offset_CC = 510h] ............................................. 1347
26-185. Input Buffer Command Request Register (IBCR) [offset_CC = 514h].......................................... 1348
26-186. Read Data Section Registers (RDDSn) [offset_CC = 600h-6FCh].............................................. 1349
26-187. Read Header Section Register 1 (RDHS1) [offset_CC = 700h] ................................................. 1350
26-188. Read Header Section Register 2 (RDHS2) [offset_CC = 704h] ................................................. 1351
26-189. Read Header Section Register 3 (RDHS3) [offset_CC = 708h] ................................................. 1352
26-190. Message Buffer Status Register (MBS) [offset_CC = 70Ch]..................................................... 1353
26-191. Output Buffer Command Mask Register (OBCM) [offset_CC = 700h].......................................... 1356
26-192. Output Buffer Command Mask Register (OBCR) [offset_CC = 714h] .......................................... 1357
27-1. DCAN Block Diagram................................................................................................... 1361
27-2. Bit Timing................................................................................................................. 1363
27-3. CAN Bit-timing Configuration .......................................................................................... 1368
27-4. Structure of a Message Object ........................................................................................ 1370
27-5. Message RAM Representation in Debug/Suspend Mode ......................................................... 1373
27-6. Message RAM Representation in RAM Direct Access Mode ..................................................... 1373
27-7. ECC RAM Representation ............................................................................................. 1374
27-8. Data Transfer Between IF1 / IF2 Registers and Message RAM.................................................. 1376
27-9. Initialization of a Transmit Object ..................................................................................... 1378
27-10. Initialization of a Single Receive Object for Data Frames ......................................................... 1378
27-11. Initialization of a Single Receive Object for Remote Frames...................................................... 1379
27-12. CPU Handling of a FIFO Buffer (Interrupt Driven) .................................................................. 1384
27-13. CAN Interrupt Topology 1 .............................................................................................. 1387
27-14. CAN Interrupt Topology 2 .............................................................................................. 1388
27-15. Local Power Down Mode Flow Diagram ............................................................................. 1390
27-16. CAN Core in Silent Mode .............................................................................................. 1391
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List of Figures SPNU563–May 2014
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