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26-62. Trigger Transfer to System Memory Set 3 (TTSMS3) [offset_TU = 90h]........................................ 1243
26-63. Trigger Transfer to System Memory Reset 3 (TTSMR3) [offset_TU = 94h]..................................... 1243
26-64. Trigger Transfer to System Memory Set 4 (TTSMS4) [offset_TU = 98h]........................................ 1244
26-65. Trigger Transfer to System Memory Reset 4 (TTSMR4) [offset_TU = 9Ch] .................................... 1244
26-66. Trigger Transfer to Communication Controller Set 1 (TTCCS1) [offset_TU = A0h] ............................ 1245
26-67. Trigger Transfer to Communication Controller Reset 1 (TTCCR1) [offset_TU = A4h]......................... 1245
26-68. Trigger Transfer to Communication Controller Set 2 (TTCCS2) [offset_TU = A8h] ............................ 1246
26-69. Trigger Transfer to Communication Controller Reset 2 (TTCCR2) [offset_TU = ACh] ........................ 1246
26-70. Trigger Transfer to Communication Controller Set 3 (TTCCS3) [offset_TU = B0h] ............................ 1247
26-71. Trigger Transfer to Communication Controller Reset 3 (TTCCR3) [offset_TU = B4h]......................... 1247
26-72. Trigger Transfer to Communication Controller Set 4 (TTCCS4) [offset_TU = B8h] ............................ 1248
26-73. Trigger Transfer to Communication Controller Reset 4 (TTCCR4) [offset_TU = BCh] ........................ 1248
26-74. Enable Transfer on Event to System Memory Set 1 (ETESMS1) [offset_TU = C0h] .......................... 1249
26-75. Enable Transfer on Event to System Memory Reset 1 (ETESMR1) [offset_TU = C4h]....................... 1249
26-76. Enable Transfer on Event to System Memory Set 2 (ETESMS2) [offset_TU = C8h] .......................... 1250
26-77. Enable Transfer on Event to System Memory Reset 2 (ETESMR2) [offset_TU = CCh] ...................... 1250
26-78. Enable Transfer on Event to System Memory Set 3 (ETESMS3) [offset_TU = D0h] .......................... 1251
26-79. Enable Transfer on Event to System Memory Reset 3 (ETESMR3) [offset_TU = D4h]....................... 1251
26-80. Enable Transfer on Event to System Memory Set 4 (ETESMS4) [offset_TU = D8h] .......................... 1252
26-81. Enable Transfer on Event to System Memory Reset 4 (ETESMR4) [offset_TU = DCh] ...................... 1252
26-82. Clear on Event to System Memory Set 1 (CESMS1) [offset_TU = E0h]......................................... 1253
26-83. Clear on Event to System Memory Reset 1 (CESMR1) [offset_TU = E4h] ..................................... 1253
26-84. Clear on Event to System Memory Set 2 (CESMS2) [offset_TU = E8h]......................................... 1254
26-85. Clear on Event to System Memory Reset 2 (CESMR2) [offset_TU = ECh] ..................................... 1254
26-86. Clear on Event to System Memory Set 3 (CESMS3) [offset_TU = F0h]......................................... 1255
26-87. Clear on Event to System Memory Reset 3 (CESMR3) [offset_TU = F4h]...................................... 1255
26-88. Clear on Event to System Memory Set 4 (CESMS4) [offset_TU = F8h]......................................... 1256
26-89. Clear on Event to System Memory Reset 4 (CESMR4) [offset_TU = FCh] ..................................... 1256
26-90. Transfer to System Memory Interrupt Enable Set 1 (TSMIES1) [offset_TU = 100h]........................... 1257
26-91. Transfer to System Memory Interrupt Enable Reset 1 (TSMIER1) [offset_TU = 104h]........................ 1257
26-92. Transfer to System Memory Interrupt Enable Set 2 (TSMIES2) [offset_TU = 108h]........................... 1258
26-93. Transfer to System Memory Interrupt Enable Reset 2 (TSMIER2) [offset_TU = 10Ch] ....................... 1258
26-94. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) [offset_TU = 110h]........................... 1259
26-95. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) [offset_TU = 114h]........................ 1259
26-96. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) [offset_TU = 118h]........................... 1260
26-97. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) [offset_TU = 11Ch] ....................... 1260
26-98. Transfer to Communication Controller Interrupt Enable Set 1 (TCCIES1) [offset_TU = 120h] ............... 1261
26-99. Transfer to Communication Controller Interrupt Enable Reset 1 (TCCIER1) [offset_TU = 124h] ............ 1261
26-100. Transfer to Communication Controller Interrupt Enable Set 2 (TCCIES2) [offset_TU = 128h].............. 1262
26-101. Transfer to Communication Controller Interrupt Enable Reset 2 (TCCIER2) [offset_TU = 12Ch] .......... 1262
26-102. Transfer to Communication Controller Interrupt Enable Set 3 (TCCIES3) [offset_TU = 130h].............. 1263
26-103. Transfer to Communication Controller Interrupt Enable Reset 3 (TCCIER3) [offset_TU = 134h]........... 1263
26-104. Transfer to Communication Controller Interrupt Enable Set 4 (TCCIES4) [offset_TU = 138h].............. 1264
26-105. Transfer to Communication Controller Interrupt Enable Reset 4 (TCCIER4) [offset_TU = 13Ch] .......... 1264
26-106. Transfer Configuration RAM (TCR) [offset_TU_RAM = 0000h - 01FFh] ....................................... 1265
26-107. ECC Information in TCR ECC Test Mode [offset_TU_RAM = 200h-3FCh].................................... 1266
26-108. Message Buffer Assignment.......................................................................................... 1267
26-109. ECC Control Register (ECC_CTRL) [offset_CC = 00h] .......................................................... 1270
26-110. ECC Diagnostic Status Register (ECCDSTAT) [offset_CC = 04h].............................................. 1271
54
List of Figures SPNU563–May 2014
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