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26-13. Structure of POC State WAKEUP .................................................................................... 1177
26-14. Timing of Wake Up Pattern ............................................................................................ 1179
26-15. State Diagram Time-Triggered Startup............................................................................... 1181
26-16. FIFO Status: Empty, Not Empty, and Overrun ...................................................................... 1192
26-17. Host Access to Message RAM ........................................................................................ 1194
26-18. Double Buffer Structure Input Buffer.................................................................................. 1195
26-19. Swapping of IBCM and IBCR Bits .................................................................................... 1195
26-20. Double Buffer Structure Output Buffer................................................................................ 1197
26-21. Swapping of OBCM and OBCR Bits.................................................................................. 1197
26-22. Access to Transient Buffer RAMs..................................................................................... 1200
26-23. Configuration Example of Message Buffers in the Message RAM ............................................... 1201
26-24. Header Section of Message Buffer in Message RAM.............................................................. 1202
26-25. Example Structure of Data Partition in Message RAM............................................................. 1204
26-26. Parity/ECC Structure.................................................................................................... 1205
26-27. ECC Generation and Check ........................................................................................... 1206
26-28. ECC Syndrome Table .................................................................................................. 1207
26-29. ECC Syndrome Table (TCR) .......................................................................................... 1207
26-30. Transfer Unit Interrupt Structure....................................................................................... 1212
26-31. Interrupt Structure ....................................................................................................... 1214
26-32. Global Static Number 0 (GSN0) [offset_TU = 00h] ................................................................. 1221
26-33. Global Static Number 1 (GSN1) [offset_TU = 04h] ................................................................. 1221
26-34. Global Control Set (GCS) [offset_TU = 10h] ........................................................................ 1222
26-35. Global Control Reset (GCR) [offset_TU = 14h] ..................................................................... 1222
26-36. Transfer Status Current Buffer (TSCB) [offset_TU = 18h] ......................................................... 1225
26-37. Last Transferred Buffer to Communication Controller (LTBCC) [offset_TU = 1Ch] ............................ 1226
26-38. Last Transferred Buffer to System Memory (LTBSM) [offset_TU = 20h] ........................................ 1226
26-39. Transfer Base Address (TBA) [offset_TU = 24h].................................................................... 1227
26-40. Next Transfer Base Address (NTBA) [offset_TU = 28h] ........................................................... 1227
26-41. Base Address of Mirrored Status (BAMS) [offset_TU = 2Ch] ..................................................... 1228
26-42. Start Address of Memory Protection (SAMP) [offset_TU = 30h].................................................. 1229
26-43. End Address of Memory Protection (EAMP) [offset_TU = 34h]................................................... 1229
26-44. Transfer to System Memory Occurred 1 (TSMO1) [offset_TU = 40h] ........................................... 1230
26-45. Transfer to System Memory Occurred 2 (TSMO2) [offset_TU = 44h] ........................................... 1230
26-46. Transfer to System Memory Occurred 3 (TSMO3) [offset_TU = 48h] ........................................... 1231
26-47. Transfer to System Memory Occurred 4 (TSMO4) [offset_TU = 4Ch] ........................................... 1231
26-48. Transfer to Communication Controller Occurred 1 (TCCO1) [offset_TU = 50h] ................................ 1232
26-49. Transfer to Communication Controller Occurred 2 (TCCO2) [offset_TU = 54h] ................................ 1232
26-50. Transfer to Communication Controller Occurred 3 (TCCO3) [offset_TU = 58h] ................................ 1233
26-51. Transfer to Communication Controller Occurred 4 (TCCO4) [offset_TU = 5Ch]................................ 1233
26-52. Transfer Occurred Offset (TOOFF) [offset_TU = 60h] ............................................................. 1234
26-53. TCR Single Bit Error Status (TSBESTAT) [offset_TU = 6Ch] ..................................................... 1235
26-54. ECC Error Address (PEADR) [offset_TU = 70h] .................................................................... 1236
26-55. Transfer Error Interrupt Flag (TEIF) [offset_TU = 74h]............................................................. 1237
26-56. Transfer Error Interrupt Enable Set (TEIRES) [offset_TU = 78h]................................................. 1239
26-57. Transfer Error Interrupt Enable Reset (TEIRER) [offset_TU = 7Ch] ............................................. 1240
26-58. Trigger Transfer to System Memory Set 1 (TTSMS1) [offset_TU = 80h]........................................ 1241
26-59. Trigger Transfer to System Memory Reset 1 (TTSMR1) [offset_TU = 84h]..................................... 1241
26-60. Trigger Transfer to System Memory Set 2 (TTSMS2) [offset_TU = 88h]........................................ 1242
26-61. Trigger Transfer to System Memory Reset 2 (TTSMR2) [offset_TU = 8Ch] .................................... 1242
53
SPNU563–May 2014 List of Figures
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