Datasheet

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20-106. DMA ECC Single Bit Error Address Register (DMAECCSBE) [offset = 230h] .................................. 768
20-107. FIFO A Status Register (FIFOASTAT) [offset = 240h] ............................................................. 769
20-108. FIFO B Status Register (FIFOBSTAT) [offset = 244h] ............................................................. 769
20-109. DMA Request Polarity Select Register (DMAREQPS1) [offset = 330h] ......................................... 770
20-110. DMA Request Polarity Select Register (DMAREQPS0) [offset = 334h] ......................................... 770
20-111. Transaction Parity Error Event Control Register (TERECTRL) [offset = 340h] ................................. 771
20-112. TER Event Flag Register (TERFLAG) [offset = 344h].............................................................. 771
20-113. TER Event Channel Offset Register (TERROFFSET) [offset = 348h] ........................................... 772
20-114. Initial Source Address Register (ISADDR) [offset = 00]............................................................ 773
20-115. Initial Destination Address Register (IDADDR) [offset = 04h] ..................................................... 773
20-116. Initial Transfer Count Register (ITCOUNT) [offset = 08h].......................................................... 774
20-117. Channel Control Register (CHCTRL) [offset = 10h] ................................................................ 774
20-118. Element Index Offset Register (EIOFF) [offset = 14h].............................................................. 776
20-119. Frame Index Offset Register (FIOFF) [offset = 18h]................................................................ 776
20-120. Current Source Address Register (CSADDR) [offset = 800h]..................................................... 777
20-121. Current Destination Address Register (CDADDR) [offset = 804h]................................................ 777
20-122. Current Transfer Count Register (CTCOUNT) [offset = 808h] .................................................... 777
21-1. EMIF Functional Block Diagram ........................................................................................ 780
21-2. Timing Waveform of SDRAM PRE Command........................................................................ 784
21-3. EMIF to 2M × 16 × 4 bank SDRAM Interface......................................................................... 784
21-4. EMIF to 512K × 16 × 2 bank SDRAM Interface ...................................................................... 785
21-5. Timing Waveform for Basic SDRAM Read Operation ............................................................... 792
21-6. Timing Waveform for Basic SDRAM Write Operation ............................................................... 793
21-7. EMIF Asynchronous Interface........................................................................................... 795
21-8. EMIF to 8-bit/16-bit Memory Interface ................................................................................. 796
21-9. Common Asynchronous Interface ...................................................................................... 796
21-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................. 800
21-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode.............................................. 802
21-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...................................... 804
21-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...................................... 806
21-14. Asynchronous Read in Page Mode .................................................................................... 807
21-15. Module ID Register (MIDR) [offset = 00] .............................................................................. 813
21-16. Asynchronous Wait Cycle Configuration Register (AWCCR) [offset = 04h] ...................................... 814
21-17. SDRAM Configuration Register (SDCR) [offset = 08h] .............................................................. 815
21-18. SDRAM Refresh Control Register (SDRCR) [offset = 0Ch]......................................................... 816
21-19. Asynchronous n Configuration Register (CEnCFG) [offset = 10h - 1Ch].......................................... 817
21-20. SDRAM Timing Register (SDTIMR) [offset = 20h] ................................................................... 818
21-21. SDRAM Self Refresh Exit Timing Register (SDSRETR) [offset = 3Ch] ........................................... 819
21-22. EMIF Interrupt Raw Register (INTRAW) [offset = 40h] .............................................................. 820
21-23. EMIF Interrupt Mask Register (INTMSK) [offset = 44h] ............................................................. 821
21-24. EMIF Interrupt Mask Set Register (INTMSKSET) [offset = 48h] ................................................... 822
21-25. EMIF Interrupt Mask Clear Register (INTMSKCLR) [offset = 4Ch] ................................................ 823
21-26. Page Mode Control Register (PMCR) [offset = 68h]................................................................. 824
21-27. Example Configuration Interface........................................................................................ 826
21-28. SDRAM Timing Register (SDTIMR).................................................................................... 827
21-29. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 828
21-30. SDRAM Refresh Control Register (SDRCR).......................................................................... 828
21-31. SDRAM Configuration Register (SDCR)............................................................................... 829
21-32. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3)) ........................................ 833
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SPNU563–May 2014 List of Figures
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