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19-5. VIM in Default State ...................................................................................................... 659
19-6. VIM in a Programmed State............................................................................................. 659
19-7. Interrupt Channel Management......................................................................................... 660
19-8. VIM Interrupt Address Memory Map ................................................................................... 661
19-9. ECC Bits Mapping ........................................................................................................ 664
19-10. Detail of the IRQ Input ................................................................................................... 665
19-11. Capture Event Sources .................................................................................................. 666
19-12. Interrupt Vector Table ECC Status Register (ECCSTAT) [offset = ECh].......................................... 670
19-13. Interrupt Vector Table ECC Control Register (ECCCTL) [offset = F0h] ........................................... 671
19-14. Uncorrectable Error Address Register (UERRADDR) [offset = F4h] .............................................. 672
19-15. Fallback Vector Address Register (FBVECADDR) [offset = F8h] .................................................. 672
19-16. Single Bit Error Address Register (SBERRADDR) [offset = FCh].................................................. 673
19-17. IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h] ...................................................... 674
19-18. FIQ Index Offset Vector Register (FIQINDEX) [offset = F04h] ..................................................... 674
19-19. FIQ/IRQ Program Control Register 0 (FIRQPR0) [offset = 10h] ................................................... 675
19-20. FIQ/IRQ Program Control Register 1 (FIRQPR1) [offset = F14h].................................................. 675
19-21. FIQ/IRQ Program Control Register 2 (FIRQPR2) [offset = 18h] ................................................... 675
19-22. FIQ/IRQ Program Control Register 3 (FIRQPR3) [offset = 1Ch] ................................................... 675
19-23. Pending Interrupt Read Location Register 0 (INTREQ0) [offset = 20h] ........................................... 676
19-24. Pending Interrupt Read Location Register 1 (INTREQ1) [offset = 24h] ........................................... 676
19-25. Pending Interrupt Read Location Register 2 (INTREQ2) [offset = 28h] ........................................... 676
19-26. Pending Interrupt Read Location Register 3 (INTREQ3) [offset = 2Ch]........................................... 676
19-27. Interrupt Enable Set Register 0 (REQENASET0) [offset = 30h].................................................... 677
19-28. Interrupt Enable Set Register 1 (REQENASET1) [offset = 34h].................................................... 677
19-29. Interrupt Enable Set Register 2 (REQENASET2) [offset = 38h].................................................... 677
19-30. Interrupt Enable Set Register 3 (REQENASET3) [offset = 3Ch] ................................................... 677
19-31. Interrupt Enable Clear Register 0 (REQENACLR0) [offset = 40h] ................................................. 678
19-32. Interrupt Enable Clear Register 1 (REQENACLR1) [offset = 44h] ................................................. 678
19-33. Interrupt Enable Clear Register 2 (REQENACLR2) [offset = 48h] ................................................. 678
19-34. Interrupt Enable Clear Register 3 (REQENACLR3) [offset = 4Ch]................................................. 678
19-35. Wake-Up Enable Set Register 0 (WAKEENASET0) [offset = 50h] ................................................ 679
19-36. Wake-Up Enable Set Register 1 (WAKEENASET1) [offset = 54h] ................................................ 679
19-37. Wake-Up Enable Set Register 2 (WAKEENASET2) [offset = 58h] ................................................ 679
19-38. Wake-Up Enable Set Register 3 (WAKEENASET3) [offset = 5Ch]................................................ 679
19-39. Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h].............................................. 680
19-40. Wake-Up Enable Clear Register 1 (WAKEENACLR1) [offset = 64h].............................................. 680
19-41. Wake-Up Enable Clear Register 2 (WAKEENACLR2) [offset = 68h].............................................. 680
19-42. Wake-Up Enable Clear Register 3 (WAKEENACLR3) [offset = 6Ch] ............................................. 680
19-43. IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h]........................................................ 681
19-44. IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h] ........................................................ 681
19-45. Capture Event Register (CAPEVT) [offset = 78h] .................................................................... 682
19-46. Interrupt Control Registers (CHANCTRL[0:31]) [offset = 80h-FCh]................................................ 683
20-1. DMA Block Diagram...................................................................................................... 687
20-2. Example of a DMA Transfer Using Frame Trigger Source.......................................................... 689
20-3. Example of a DMA Transfer Using Block Trigger Source ........................................................... 689
20-4. DMA Request Mapping and Control Packet Organization .......................................................... 691
20-5. Control Packet Organization and Memory Map ...................................................................... 691
20-6. DMA Transfer Example 1................................................................................................ 693
20-7. DMA Indexing Example 1................................................................................................ 693
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List of Figures SPNU563–May 2014
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