Datasheet

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16-39. ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) [offset = 94h]......................................... 570
16-40. ESM Status Register 7 (ESMSR7) [offset = 98h] .................................................................... 571
17-1. RTI Block Diagram........................................................................................................ 574
17-2. Counter Block Diagram .................................................................................................. 575
17-3. Compare Unit Block Diagram (shows only 1 of 4 blocks for simplification)....................................... 577
17-4. Timebase Control ......................................................................................................... 578
17-5. Clock Detection Scheme................................................................................................. 578
17-6. Switch to NTUx............................................................................................................ 579
17-7. Missing NTUx Signal Example.......................................................................................... 580
17-8. Digital Watchdog.......................................................................................................... 580
17-9. DWD Operation ........................................................................................................... 581
17-10. Digital Windowed Watchdog Timing Example ........................................................................ 582
17-11. Digital Windowed Watchdog Operation Example (25% Window) .................................................. 582
17-12. RTI Global Control Register (RTIGCTRL) [offset = 00].............................................................. 585
17-13. RTI Timebase Control Register (RTITBCTRL) [offset = 04h]....................................................... 586
17-14. RTI Capture Control Register (RTICAPCTRL) [offset = 08h] ....................................................... 587
17-15. RTI Compare Control Register (RTICOMPCTRL) [offset = 0Ch]................................................... 588
17-16. RTI Free Running Counter 0 Register (RTIFRC0) [offset = 10h]................................................... 589
17-17. RTI Up Counter 0 Register (RTIUC0) [offset = 14h] ................................................................. 589
17-18. RTI Compare Up Counter 0 Register (RTICPUC0) [offset = 18h] ................................................. 590
17-19. RTI Capture Free Running Counter 0 Register (RTICAFRC0) [offset = 20h] .................................... 590
17-20. RTI Capture Up Counter 0 Register (RTICAUC0) [offset = 24h] ................................................... 591
17-21. RTI Free Running Counter 1 Register (RTIFRC1) [offset = 30h]................................................... 591
17-22. RTI Up Counter 1 Register (RTIUC1) [offset = 34h] ................................................................. 592
17-23. RTI Compare Up Counter 1 Register (RTICPUC1) [offset = 38h] ................................................. 593
17-24. RTI Capture Free Running Counter 1 Register (RTICAFRC1) [offset = 40h] .................................... 594
17-25. RTI Capture Up Counter 1 Register (RTICAUC1) [offset = 44h] ................................................... 594
17-26. RTI Compare 0 Register (RTICOMP0) [offset = 50h]................................................................ 595
17-27. RTI Update Compare 0 Register (RTIUDCP0) [offset = 54h]....................................................... 595
17-28. RTI Compare 1 Register (RTICOMP1) [offset = 58h]................................................................ 596
17-29. RTI Update Compare 1 Register (RTIUDCP1) [offset = 5Ch] ...................................................... 596
17-30. RTI Compare 2 Register (RTICOMP2) [offset = 60h]................................................................ 597
17-31. RTI Update Compare 2 Register (RTIUDCP2) [offset = 64h]....................................................... 597
17-32. RTI Compare 3 Register (RTICOMP3) [offset = 68h]................................................................ 598
17-33. RTI Update Compare 3 Register (RTIUDCP3) [offset = 6Ch] ...................................................... 598
17-34. RTI Timebase Low Compare Register (RTITBLCOMP) [offset = 70h] ............................................ 599
17-35. RTI Timebase High Compare Register (RTITBHCOMP) [offset = 74h] ........................................... 599
17-36. RTI Set Interrupt Control Register (RTISETINTENA) [offset = 80h] ............................................... 600
17-37. RTI Clear Interrupt Control Register (RTICLEARINTENA) [offset = 84h] ......................................... 602
17-38. RTI Interrupt Flag Register (RTIINTFLAG) [offset = 88h] ........................................................... 604
17-39. Digital Watchdog Control Register (RTIDWDCTRL) [offset = 90h] ................................................ 605
17-40. Digital Watchdog Preload Register (RTIDWDPRLD) [offset = 94h]................................................ 606
17-41. Watchdog Status Register (RTIWDSTATUS) [offset = 98h] ........................................................ 607
17-42. RTI Watchdog Key Register (RTIDWDKEY) [offset = 9Ch]......................................................... 608
17-43. RTI Watchdog Down Counter Register (RTIDWDCNTR) [offset = A0h] .......................................... 609
17-44. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) [offset = A4h]............................ 609
17-45. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) [offset = A8h]....................... 610
17-46. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) [offset = ACh] ........................... 611
17-47. RTI Compare 0 Clear Register (RTICMP0CLR) [offset = B0h]..................................................... 612
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List of Figures SPNU563–May 2014
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