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11-9. MPU Error Address Register (MPUERRADDR) (offset = 14h) ..................................................... 466
11-10. MPU Control Register 1 (MPUCTRL1) (offset = 20h)................................................................ 466
11-11. MPU Control Register 2 (MPUCTRL2) (offset = 24h)................................................................ 467
11-12. MPU Type Register (MPUTYPE) (offset = 2Ch)...................................................................... 468
11-13. MPU Region Base Address Register (MPUREGBASE) (offset = 30h)............................................ 469
11-14. MPU Region Size and Enable Register (MPUREGSENA) (offset = 34h)......................................... 469
11-15. MPU Region Access Control Register (MPUREGACR) (offset = 38h) ............................................ 471
11-16. MPU Region Number Register (MPUREGNUM) (offset = 3Ch).................................................... 472
12-1. EPC System Block Diagram............................................................................................. 475
12-2. EPC REVID Register (EPCREVID) (offset = 00h).................................................................... 479
12-3. EPC Control Register (EPCCNTRL) (offset = 04h) .................................................................. 480
12-4. Uncorrectable Error Status Register (UERRSTAT) (offset = 08h) ................................................. 481
12-5. EPC Error Status Register (EPCERRSTAT) (offset = 0Ch)......................................................... 482
12-6. FIFO Full Status Register (FIFOFULLSTAT) (offset = 10h)......................................................... 483
12-7. IP Interface FIFO Overflow Status Register (OVRFLWSTAT) (offset = 14h)..................................... 484
12-8. CAM Index Available Status Register (CAMAVAILSTAT) (offset = 18h).......................................... 484
12-9. Uncorrectable Error Address Register n (UERR_ADDR) (offset = 20h-24h) ..................................... 485
12-10. CAM Content Update Register n (CAM_CONTENT) (offset = A0h-11Ch)........................................ 485
12-11. CAM Index Registers (CAM_INDEXn) (offset = 200h-21Ch) ....................................................... 486
13-1. Block Diagram............................................................................................................. 489
13-2. CPU Input Inversion Scheme ........................................................................................... 494
13-3. CCM-R5F Status Register 1 (CCMSR1) (Offset = 00h) ............................................................. 498
13-4. CCM-R5F Key Register 1 (CCMKEYR1) (Offset = 04h) ............................................................ 499
13-5. CCM-R5F Status Register 2 (CCMSR2) (Offset = 08h) ............................................................. 500
13-6. CCM-R5F Key Register 2 (CCMKEYR2) (Offset = 0Ch) ............................................................ 501
13-7. CCM-R5F Status Register 3 (CCMSR3) (Offset = 10h) ............................................................. 502
13-8. CCM-R5F Key Register 3 (CCMKEYR3) (Offset = 14h) ............................................................ 503
13-9. CCM-R5F Polarity Control Register (CCMPOLCNTRL) (Offset = 18h) ........................................... 503
13-10. CCM-R5F Status Register 4 (CCMSR4) (Offset = 1Ch)............................................................. 504
13-11. CCM-R5F Key Register 4 (CCMKEYR4) (Offset = 20h) ............................................................ 505
13-12. CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0) (Offset = 24h).................................... 506
14-1. Clock Path from Oscillator through PLL to Device ................................................................... 509
14-2. Clock Generation Path ................................................................................................... 510
14-3. Oscillator Implementation................................................................................................ 511
14-4. Operation of the FM-PLL Module....................................................................................... 515
14-5. PLL Slip Detection and Reset/Bypass Block Diagram............................................................... 521
14-6. SSW PLL BIST Control Register 1 (SSWPLL1) [offset = 24h] ..................................................... 525
14-7. SSW PLL BIST Control Register 2 (SSWPLL2) [offset = 28h] ..................................................... 526
14-8. SSW PLL BIST Control Register 3 (SSWPLL3) [offset = 2Ch] ..................................................... 527
14-9. Basic PLL Circuit.......................................................................................................... 528
14-10. PFD Timing ................................................................................................................ 528
14-11. PLL Modulation Block Diagram ......................................................................................... 529
14-12. Frequency versus Time .................................................................................................. 530
15-1. DCC Operation............................................................................................................ 533
15-2. Counter Relationship ..................................................................................................... 535
15-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting ........................................... 535
15-4. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting............................................ 536
15-5. Clock1 Not Present - Results in an Error and Stops Counting ..................................................... 536
15-6. Clock0 Not Present - Results in an Error and Stops Counting ..................................................... 537
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List of Figures SPNU563–May 2014
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