Datasheet

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7-16. Primary Address Tag Register (FPRIM_ADD_TAG) (offset = 28h)................................................ 355
7-17. Duplicate Address Tag Register (FDUP_ADD_TAG) (offset = 2Ch) .............................................. 355
7-18. Flash Bank Protection Register (FBPROT) (offset = 30h) .......................................................... 356
7-19. Flash Bank Sector Enable Register (FBSE) (offset = 34h) ......................................................... 356
7-20. Flash Bank Busy Register (FBBUSY) (offset = 38h)................................................................. 357
7-21. Flash Bank Access Control Register (FBAC) (offset = 3Ch)........................................................ 357
7-22. Flash Bank Power Mode Register (FBPWRMODE) (offset = 40h)................................................. 358
7-23. Flash Bank/Pump Ready Register (FBPRDY) (offset = 44h) ....................................................... 359
7-24. Flash Pump Access Control Register 1 (FPAC1) (offset = 48h) ................................................... 360
7-25. Flash Module Access Control Register (FMAC) (offset = 50h) ..................................................... 361
7-26. Flash Module Status Register (FMSTAT) (offset = 54h) ............................................................ 362
7-27. EEPROM Emulation Data MSW Register (FEMU_DMSW) (offset = 58h)........................................ 364
7-28. EEPROM Emulation Data LSW Register (FEMU_DLSW) (offset = 5Ch) ......................................... 364
7-29. EEPROM Emulation ECC Register (FEMU_ECC) (offset = 60h) .................................................. 365
7-30. Flash Lock Register (FLOCK) (offset = 64h).......................................................................... 365
7-31. Diagnostic Control Register (FDIAGCTRL) (offset = 6Ch) .......................................................... 366
7-32. Raw Address Register (FRAW_ADDR) (offset = 74h)............................................................... 367
7-33. Parity Override Register (FPAR_OVR) (offset = 7Ch)............................................................... 368
7-34. Reset Configuration Valid Register (RCR_VALID) (offset = B4h).................................................. 369
7-35. Crossbar Access Time Threshold Register (ACC_THRESHOLD) (offset = B8h)................................ 369
7-36. Flash Error Detection and Correction Sector Disable Register 2 (FEDACSDIS2) (offset = C0h).............. 370
7-37. Lower Word of Reset Configuration Read Register (RCR_VALUE0) (offset = D0h) ............................ 371
7-38. Upper Word of Reset Configuration Read Register (RCR_VALUE1) (offset = D4h) ............................ 371
7-39. FSM Register Write Enable Register (FSM_WR_ENA) (offset = 288h)........................................... 372
7-40. EEPROM Emulation Configuration Register (EEPROM_CONFIG) (offset = 2B8h) ............................. 372
7-41. FSM Sector Register 1 (FSM_SECTOR1) (offset = 2C0h) ......................................................... 373
7-42. FSM Sector Register 2 (FSM_SECTOR2) (offset = 2C4h) ......................................................... 373
7-43. Flash Bank Configuration Register (FCFG_BANK) (offset = 400h)................................................ 374
7-44. POM Global Control Register (POMGLBCTRL) (offset = 00h) ..................................................... 375
7-45. POM Revision ID Register (POMREV) (offset = 04h) ............................................................... 376
7-46. POM Flag Register (POMFLG) (offset = 0Ch)........................................................................ 376
7-47. POM Region Start Address Register (POMPROGSTARTx) (offset = 200h, 210h,..)............................ 377
7-48. POM Overlay Region Start Address Register (POMOVLSTARTx) (offset = 204h, 214h,...) ................... 377
7-49. POM Region Size Register (POMREGSIZEx) (offset = 208h, 218h, ...) .......................................... 378
8-1. RAM Memory Map........................................................................................................ 381
8-2. L2RAMW Module Control Register (RAMCTRL) (offset = 00h) .................................................... 385
8-3. L2RAMW Module Error Status Register (RAMERRSTATUS) (offset = 10h) ..................................... 387
8-4. L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H) (offset = 24h) .................. 390
8-5. L2RAMW Diagnostic Vector Low Register (DIAG_DATA_VECTOR_L) (offset = 28h).......................... 390
8-6. L2RAMW Diagnostic ECC Vector Register (DIAG_ECC) (offset = 2Ch).......................................... 391
8-7. L2RAMW Module Test Mode Control Register (RAMTEST) (offset = 30h)....................................... 392
8-8. L2RAMW RAM Address Decode Vector Test Register (RAMADDRDEC_VECT) (offset = 38h) .............. 393
8-9. L2RAMW Memory Initialization Domain Register (MEMINIT_DOMAIN) (offset = 3Ch)......................... 394
8-10. L2RAMW Bank to Domain Mapping Register0 (BANK_DOMAIN_MAP0) (offset = 44h) ....................... 395
8-11. L2RAMW Bank to Domain Mapping Register1 (BANK_DOMAIN_MAP1) (offset = 48h) ....................... 396
9-1. PBIST Block Diagram .................................................................................................... 398
9-2. PBIST Memory Self-Test Flow Diagram............................................................................... 400
9-3. RAM Configuration Register (RAMT) [offset = 0160h]............................................................... 405
9-4. Datalogger Register (DLR) [offset = 0164h]........................................................................... 406
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List of Figures SPNU563–May 2014
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