Datasheet

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2-46. RAM Control Register (RAMGCR) (offset = C0h) .................................................................... 188
2-47. Bus Matrix Module Control Register 1 (BMMCR) (offset = C4h) ................................................... 189
2-48. CPU Reset Control Register (CPURSTCR) (offset = CCh) ........................................................ 189
2-49. Clock Control Register (CLKCNTL) (offset = D0h)................................................................... 190
2-50. ECP Control Register (ECPCNTL) (offset = D4h).................................................................... 191
2-51. DEV Parity Control Register 1 (DEVCR1) (offset = DCh) ........................................................... 192
2-52. System Exception Control Register (SYSECR) (offset = E0h) ..................................................... 192
2-53. System Exception Status Register (SYSESR) (offset = E4h)....................................................... 193
2-54. System Test Abort Status Register (SYSTASR) (offset = E8h) ................................................... 195
2-55. Global Status Register (GLBSTAT) (offset = ECh)................................................................... 196
2-56. Device Identification Register (DEVID) (offset = F0h) ............................................................... 197
2-57. Software Interrupt Vector Register (SSIVEC) (offset = F4h)........................................................ 198
2-58. System Software Interrupt Flag Register (SSIF) (offset = F8h) .................................................... 199
2-59. PLL Control Register 3 (PLLCTL3) (offset = 00h).................................................................... 201
2-60. CPU Logic BIST Clock Prescaler (STCLKDIV) (offset = 08h) ...................................................... 202
2-61. ECP Control Register 1 (ECPCNTL1) (offset = 28h) ................................................................ 203
2-62. Clock 2 Control Register (CLK2CNTRL) (offset = 3Ch) ............................................................. 204
2-63. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) [offset = 40h] ....................... 205
2-64. HCLK Control Register (HCLKCNTL) (offset = 54h) ................................................................ 207
2-65. Clock Slip Control Register (CLKSLIP) (offset = 70h) .............................................................. 208
2-66. IP ECC Error Enable Register (IP1ECCERREN) (offset = 78h) ................................................... 209
2-67. EFUSE Controller Control Register (EFC_CTLREG) (offset = ECh) .............................................. 210
2-68. Die Identification Register, Lower Word (DIEIDL_REG0) [offset = F0h] .......................................... 210
2-69. Die Identification Register, Upper Word (DIEIDH_REG1) [offset = F4h] .......................................... 211
2-70. Die Identification Register, Lower Word (DIEIDL_REG2) [offset = F8h] .......................................... 211
2-71. Die Identification Register, Upper Word (DIEIDH_REG3) [offset = FCh] ......................................... 211
2-72. Peripheral Memory Protection Set Register 0 (PMPROTSET0) (offset = 00h)................................... 218
2-73. Peripheral Memory Protection Set Register 1 (PMPROTSET1) (offset = 04h)................................... 218
2-74. Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) (offset = 10h) ................................ 219
2-75. Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) (offset = 14h) ................................ 219
2-76. Peripheral Protection Set Register 0 (PPROTSET0) (offset = 20h) ............................................... 220
2-77. Peripheral Protection Set Register 1 (PPROTSET1) (offset = 24h) ............................................... 221
2-78. Peripheral Protection Set Register 2 (PPROTSET2) (offset = 28h) ............................................... 221
2-79. Peripheral Protection Set Register 3 (PPROTSET3) (offset = 2Ch) ............................................... 222
2-80. Peripheral Protection Clear Register 0 (PPROTCLR0) (offset = 40h) ............................................. 222
2-81. Peripheral Protection Clear Register 1 (PPROTCLR1) (offset = 44h) ............................................. 223
2-82. Peripheral Protection Clear Register 2 (PPROTCLR2) (offset = 48h) ............................................. 223
2-83. Peripheral Protection Clear Register 3 (PPROTCLR3) (offset = 4Ch) ............................................ 224
2-84. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) (offset = 60h)......................... 224
2-85. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) (offset = 64h)......................... 225
2-86. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) (offset = 70h) ...................... 225
2-87. Peripheral Memory Power-Down Clear Register 1 (PCSPWRDWNCLR1) (offset = 74h) ...................... 226
2-88. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) (offset = 80h) ..................................... 227
2-89. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) (offset = 84h) ..................................... 228
2-90. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) (offset = 88h) ..................................... 228
2-91. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) (offset = 8Ch)..................................... 229
2-92. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) (offset = A0h) .................................. 229
2-93. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) (offset = A4h) .................................. 230
2-94. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) (offset = A8h) .................................. 230
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SPNU563–May 2014 List of Figures
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