Datasheet

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37.3.3 RTP Global Status Register (RTPGSR).................................................................... 2102

37.3.4 RTP RAM 1 Trace Region Registers (RTPRAM1REG[1:2]) ............................................ 2104

37.3.5 RTP RAM 2 Trace Region Registers (RTPRAM2REG[1:2]) ............................................ 2105

37.3.6 RTP RAM 3 Trace Region Registers (RTPRAM3REG[1:2]) ............................................ 2106

37.3.7 RTP Peripheral Trace Region Registers (RTPPERREG[1:2]) .......................................... 2108

37.3.8 RTP Direct Data Mode Write Register (RTPDDMW)..................................................... 2109

37.3.9 RTP Pin Control 0 Register (RTPPC0)..................................................................... 2110

37.3.10 RTP Pin Control 1 Register (RTPPC1) ................................................................... 2111

37.3.11 RTP Pin Control 2 Register (RTPPC2) ................................................................... 2112

37.3.12 RTP Pin Control 3 Register (RTPPC3) ................................................................... 2113

37.3.13 RTP Pin Control 4 Register (RTPPC4) ................................................................... 2114

37.3.14 RTP Pin Control 5 Register (RTPPC5) ................................................................... 2115

37.3.15 RTP Pin Control 6 Register (RTPPC6) ................................................................... 2116

37.3.16 RTP Pin Control 7 Register (RTPPC7) ................................................................... 2118

37.3.17 RTP Pin Control 8 Register (RTPPC8) ................................................................... 2119

38 eFuse Controller ............................................................................................................. 2120

38.1 Overview.................................................................................................................. 2121

38.2 Introduction............................................................................................................... 2121

38.3 eFuse Controller Testing ............................................................................................... 2121

38.3.1 eFuse Controller Connections to ESM ..................................................................... 2121

38.3.2 Checking for eFuse Errors After Power Up................................................................ 2121

38.4 eFuse Controller Registers............................................................................................. 2124

38.4.1 EFC Boundary Control Register (EFCBOUND)........................................................... 2124

38.4.2 EFC Pins Register (EFCPINS) .............................................................................. 2126

38.4.3 EFC Error Status Register (EFCERRSTAT)............................................................... 2127

38.4.4 EFC Self Test Cycles Register (EFCSTCY)............................................................... 2127

38.4.5 EFC Self Test Signature Register (EFCSTSIG) .......................................................... 2128

SPNU563–May 2014 Contents

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