Datasheet

www.ti.com
35.4.5 Trip-Zone Submodule Registers ............................................................................ 2018
35.4.6 Event-Trigger Submodule Registers........................................................................ 2026
35.4.7 PWM-Chopper Submodule Register........................................................................ 2032
35.4.8 Digital Compare Submodule Registers..................................................................... 2034
36 Data Modification Module (DMM)....................................................................................... 2041
36.1 Overview.................................................................................................................. 2042
36.1.1 Features ........................................................................................................ 2042
36.1.2 Block Diagram ................................................................................................. 2042
36.2 Module Operation ....................................................................................................... 2043
36.2.1 Data Format.................................................................................................... 2043
36.2.2 Data Port ....................................................................................................... 2045
36.2.3 Error Handling ................................................................................................. 2046
36.2.4 Interrupts ....................................................................................................... 2047
36.3 Control Registers........................................................................................................ 2048
36.3.1 DMM Global Control Register (DMMGLBCTRL).......................................................... 2049
36.3.2 DMM Interrupt Set Register (DMMINTSET) ............................................................... 2051
36.3.3 DMM Interrupt Clear Register (DMMINTCLR) ............................................................ 2055
36.3.4 DMM Interrupt Level Register (DMMINTLVL) ............................................................. 2060
36.3.5 DMM Interrupt Flag Register (DMMINTFLG).............................................................. 2062
36.3.6 DMM Interrupt Offset 1 Register (DMMOFF1) ............................................................ 2066
36.3.7 DMM Interrupt Offset 2 Register (DMMOFF2) ............................................................ 2067
36.3.8 DMM Direct Data Mode Destination Register (DMMDDMDEST)....................................... 2068
36.3.9 DMM Direct Data Mode Blocksize Register (DMMDDMBL)............................................. 2068
36.3.10 DMM Direct Data Mode Pointer Register (DMMDDMPT) .............................................. 2069
36.3.11 DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) ..................................... 2069
36.3.12 DMM Destination x Region 1 (DMMDESTxREG1)...................................................... 2070
36.3.13 DMM Destination x Blocksize 1 (DMMDESTxBL1) ..................................................... 2071
36.3.14 DMM Destination x Region 2 (DMMDESTxREG2)...................................................... 2072
36.3.15 DMM Destination x Blocksize 2 (DMMDESTxBL2) ..................................................... 2073
36.3.16 DMM Pin Control 0 (DMMPC0) ............................................................................ 2074
36.3.17 DMM Pin Control 1 (DMMPC1) ............................................................................ 2075
36.3.18 DMM Pin Control 2 (DMMPC2) ............................................................................ 2077
36.3.19 DMM Pin Control 3 (DMMPC3) ............................................................................ 2078
36.3.20 DMM Pin Control 4 (DMMPC4) ............................................................................ 2079
36.3.21 DMM Pin Control 5 (DMMPC5) ............................................................................ 2081
36.3.22 DMM Pin Control 6 (DMMPC6) ............................................................................ 2082
36.3.23 DMM Pin Control 7 (DMMPC7) ............................................................................ 2084
36.3.24 DMM Pin Control 8 (DMMPC8) ............................................................................ 2085
37 RAM Trace Port (RTP)...................................................................................................... 2087
37.1 Overview.................................................................................................................. 2088
37.1.1 Features ........................................................................................................ 2088
37.1.2 Block Diagram ................................................................................................. 2089
37.2 Module Operation ....................................................................................................... 2090
37.2.1 Trace Mode .................................................................................................... 2090
37.2.2 Direct Data Mode (DDM)..................................................................................... 2092
37.2.3 Trace Regions ................................................................................................. 2092
37.2.4 Overflow/Empty Handling .................................................................................... 2094
37.2.5 Signal Description............................................................................................. 2094
37.2.6 Data Rate ...................................................................................................... 2095
37.2.7 GIO Function................................................................................................... 2096
37.3 RTP Control Registers.................................................................................................. 2096
37.3.1 RTP Global Control Register (RTPGLBCTRL)............................................................ 2097
37.3.2 RTP Trace Enable Register (RTPTRENA) ................................................................ 2100
30
Contents SPNU563–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated