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32.3.9 EMAC Control Module Receive Interrupt Status Registers (C0RXSTAT) ............................. 1795
32.3.10 EMAC Control Module Transmit Interrupt Status Registers (C0TXSTAT) ........................... 1796
32.3.11 EMAC Control Module Miscellaneous Interrupt Status Registers (C0MISCSTAT) ................. 1797
32.3.12 EMAC Control Module Receive Interrupts Per Millisecond Registers (C0RXIMAX)................ 1798
32.3.13 EMAC Control Module Transmit Interrupts Per Millisecond Registers (C0TXIMAX) ............... 1799
32.4 MDIO Registers.......................................................................................................... 1800
32.4.1 MDIO Revision ID Register (REVID) ....................................................................... 1800
32.4.2 MDIO Control Register (CONTROL) ....................................................................... 1801
32.4.3 PHY Acknowledge Status Register (ALIVE)............................................................... 1802
32.4.4 PHY Link Status Register (LINK) ........................................................................... 1802
32.4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)........................... 1803
32.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ......................... 1804
32.4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW).................. 1805
32.4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................ 1806
32.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) .............. 1807
32.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)....... 1808
32.4.11 MDIO User Access Register 0 (USERACCESS0) ...................................................... 1809
32.4.12 MDIO User PHY Select Register 0 (USERPHYSEL0).................................................. 1810
32.4.13 MDIO User Access Register 1 (USERACCESS1) ...................................................... 1811
32.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1).................................................. 1812
32.5 EMAC Module Registers ............................................................................................... 1813
32.5.1 Transmit Revision ID Register (TXREVID) ................................................................ 1816
32.5.2 Transmit Control Register (TXCONTROL)................................................................. 1816
32.5.3 Transmit Teardown Register (TXTEARDOWN)........................................................... 1817
32.5.4 Receive Revision ID Register (RXREVID)................................................................. 1817
32.5.5 Receive Control Register (RXCONTROL) ................................................................. 1818
32.5.6 Receive Teardown Register (RXTEARDOWN) ........................................................... 1818
32.5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ................................... 1819
32.5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................. 1820
32.5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................... 1821
32.5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ....................................... 1822
32.5.11 MAC Input Vector Register (MACINVECTOR) .......................................................... 1823
32.5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) ........................................... 1824
32.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW).................................. 1825
32.5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................ 1826
32.5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) .............................................. 1827
32.5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)........................................ 1828
32.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................... 1829
32.5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED).................................. 1829
32.5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)................................................ 1830
32.5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ......................................... 1830
32.5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......... 1831
32.5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................. 1833
32.5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ................................................ 1834
32.5.24 Receive Maximum Length Register (RXMAXLEN)...................................................... 1834
32.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)................................................. 1835
32.5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)................. 1835
32.5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH) 1836
32.5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) ........ 1836
32.5.29 MAC Control Register (MACCONTROL) ................................................................. 1837
32.5.30 MAC Status Register (MACSTATUS)..................................................................... 1839
32.5.31 Emulation Control Register (EMCONTROL) ............................................................. 1841
32.5.32 FIFO Control Register (FIFOCONTROL)................................................................. 1841
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SPNU563–May 2014 Contents
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