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31.6.10 I2C Mode Register (I2CMDR).............................................................................. 1727
31.6.11 I2C Interrupt Vector Register (I2CIVR) ................................................................... 1730
31.6.12 I2C Extended Mode Register (I2CEMDR)................................................................ 1731
31.6.13 I2C Prescale Register (I2CPSC) .......................................................................... 1731
31.6.14 I2C Peripheral ID Register 1 (I2CPID1) .................................................................. 1732
31.6.15 I2C Peripheral ID Register 2 (I2CPID2) .................................................................. 1732
31.6.16 I2C DMA Control Register (I2CDMACR) ................................................................. 1733
31.6.17 I2C Pin Function Register (I2CPFNC) .................................................................... 1733
31.6.18 I2C Pin Direction Register (I2CPDIR)..................................................................... 1734
31.6.19 I2C Data Input Register (I2CDIN) ......................................................................... 1734
31.6.20 I2C Data Output Register (I2CDOUT) .................................................................... 1735
31.6.21 I2C Data Set Register (I2CDSET)......................................................................... 1735
31.6.22 I2C Data Clear Register (I2CDCLR) ...................................................................... 1736
31.6.23 I2C Pin Open Drain Register (I2CPDR) .................................................................. 1736
31.6.24 I2C Pull Disable Register (I2CPDIS) ...................................................................... 1737
31.6.25 I2C Pull Select Register (I2CPSEL)....................................................................... 1737
31.6.26 I2C Pins Slew Rate Select Register (I2CSRS) .......................................................... 1738
31.7 Sample Waveforms ..................................................................................................... 1739
32 EMAC/MDIO Module ........................................................................................................ 1740
32.1 Introduction............................................................................................................... 1741
32.1.1 Purpose of the Peripheral .................................................................................... 1741
32.1.2 Features ........................................................................................................ 1741
32.1.3 Functional Block Diagram.................................................................................... 1742
32.1.4 Industry Standard(s) Compliance Statement .............................................................. 1743
32.2 Architecture .............................................................................................................. 1743
32.2.1 Clock Control .................................................................................................. 1743
32.2.2 Memory Map................................................................................................... 1743
32.2.3 Signal Descriptions............................................................................................ 1744
32.2.4 MII / RMII Signal Multiplexing Control ...................................................................... 1747
32.2.5 Ethernet Protocol Overview.................................................................................. 1748
32.2.6 Programming Interface ....................................................................................... 1749
32.2.7 EMAC Control Module........................................................................................ 1760
32.2.8 MDIO Module .................................................................................................. 1761
32.2.9 EMAC Module ................................................................................................. 1766
32.2.10 MAC Interface................................................................................................ 1768
32.2.11 Packet Receive Operation.................................................................................. 1772
32.2.12 Packet Transmit Operation ................................................................................. 1777
32.2.13 Receive and Transmit Latency............................................................................. 1778
32.2.14 Transfer Node Priority....................................................................................... 1778
32.2.15 Reset Considerations ....................................................................................... 1779
32.2.16 Initialization ................................................................................................... 1780
32.2.17 Interrupt Support............................................................................................. 1782
32.2.18 Power Management ......................................................................................... 1786
32.2.19 Emulation Considerations .................................................................................. 1786
32.3 EMAC Control Module Registers...................................................................................... 1787
32.3.1 EMAC Control Module Revision ID Register (REVID) ................................................... 1788
32.3.2 EMAC Control Module Software Reset Register (SOFTRESET)....................................... 1788
32.3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) .................................... 1789
32.3.4 EMAC Control Module Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN) ....... 1790
32.3.5 EMAC Control Module Receive Interrupt Enable Registers (C0RXEN) ............................... 1791
32.3.6 EMAC Control Module Transmit Interrupt Enable Registers (C0TXEN) ............................... 1792
32.3.7 EMAC Control Module Miscellaneous Interrupt Enable Registers (C0MISCEN) ..................... 1793
32.3.8 EMAC Control Module Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT) ..... 1794
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Contents SPNU563–May 2014
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