Datasheet

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30.7.18 SCI Pin I/O Control Register 5 (SCIPIO5) ............................................................... 1695
30.7.19 SCI Pin I/O Control Register 6 (SCIPIO6) ............................................................... 1696
30.7.20 SCI Pin I/O Control Register 7 (SCIPIO7) ............................................................... 1697
30.7.21 SCI Pin I/O Control Register 8 (SCIPIO8) ............................................................... 1697
30.7.22 Input/Output Error Enable (IODFTCTRL) Register ..................................................... 1698
30.8 GPIO Functionality ...................................................................................................... 1700
30.8.1 GPIO Functionality ............................................................................................ 1700
30.8.2 Under Reset ................................................................................................... 1700
30.8.3 Out of Reset ................................................................................................... 1701
30.8.4 Open-Drain Feature Enabled on a Pin ..................................................................... 1701
30.8.5 Summary ....................................................................................................... 1701
31 Inter-Integrated Circuit (I2C) Module.................................................................................. 1702
31.1 Overview.................................................................................................................. 1703
31.1.1 Introduction to the I2C Module .............................................................................. 1703
31.1.2 Functional Overview .......................................................................................... 1704
31.1.3 Clock Generation.............................................................................................. 1706
31.2 I2C Module Operation .................................................................................................. 1707
31.2.1 Input and Output Voltage Levels ............................................................................ 1707
31.2.2 I2C Module Reset Conditions ............................................................................... 1707
31.2.3 I2C Module Data Validity .................................................................................... 1707
31.2.4 I2C Module Start and Stop Conditions ..................................................................... 1708
31.2.5 Serial Data Formats........................................................................................... 1708
31.2.6 NACK Bit Generation ......................................................................................... 1710
31.3 I2C Operation Modes ................................................................................................... 1711
31.3.1 Master Transmitter Mode .................................................................................... 1711
31.3.2 Master Receiver Mode ....................................................................................... 1711
31.3.3 Slave Transmitter Mode...................................................................................... 1711
31.3.4 Slave Receiver Mode ........................................................................................ 1711
31.3.5 Low Power Mode.............................................................................................. 1712
31.3.6 Free Run Mode................................................................................................ 1712
31.3.7 Ignore NACK Mode .......................................................................................... 1712
31.4 I2C Module Integrity..................................................................................................... 1713
31.4.1 Arbitration ...................................................................................................... 1713
31.4.2 I2C Clock Generation and Synchronization ............................................................... 1714
31.4.3 Prescaler ....................................................................................................... 1714
31.4.4 Noise Filter ..................................................................................................... 1714
31.5 Operational Information................................................................................................. 1715
31.5.1 I2C Module Interrupts......................................................................................... 1715
31.5.2 DMA Controller Events ....................................................................................... 1716
31.5.3 I2C Enable/Disable............................................................................................ 1716
31.5.4 General Purpose I/O.......................................................................................... 1716
31.5.5 Pull Up/Pull Down Function.................................................................................. 1717
31.5.6 Open Drain Function.......................................................................................... 1717
31.6 I2C Control Registers................................................................................................... 1718
31.6.1 I2C Own Address Manager (I2COAR) ..................................................................... 1719
31.6.2 I2C Interrupt Mask Register (I2CIMR)...................................................................... 1720
31.6.3 I2C Status Register (I2CSTR) ............................................................................... 1721
31.6.4 I2C Clock Divider Low Register (I2CCKL) ................................................................. 1724
31.6.5 I2C Clock Control High Register (I2CCKH)................................................................ 1724
31.6.6 I2C Data Count Register (I2CCNT)......................................................................... 1725
31.6.7 I2C Data Receive Register (I2CDRR) ...................................................................... 1725
31.6.8 I2C Slave Address Register (I2CSAR) ..................................................................... 1726
31.6.9 I2C Data Transmit Register (I2CDXR) ..................................................................... 1726
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SPNU563–May 2014 Contents
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