Datasheet
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28.5.1 Example of Parity Memory Organization................................................................... 1552
28.5.2 Example of ECC Memory Organization .................................................................... 1553
28.6 MibSPI Pin Timing Parameters........................................................................................ 1554
28.6.1 Master Mode Timings for SPI/MibSPI ...................................................................... 1554
28.6.2 Slave Mode Timings for SPI/MibSPI........................................................................ 1556
28.6.3 Master Mode Timing Parameter Details.................................................................... 1557
28.6.4 Slave Mode Timing Parameter Details ..................................................................... 1557
29 Serial Communication Interface (SCI)/Local Interconnect Network (LIN) Module..................... 1558
29.1 Introduction and Features.............................................................................................. 1559
29.1.1 SCI Features................................................................................................... 1559
29.1.2 LIN Features ................................................................................................... 1560
29.1.3 Block Diagram ................................................................................................. 1561
29.2 SCI ........................................................................................................................ 1564
29.2.1 SCI Communication Formats................................................................................ 1564
29.2.2 SCI Interrupts .................................................................................................. 1572
29.2.3 SCI DMA Interface ............................................................................................ 1575
29.2.4 SCI Configurations ............................................................................................ 1576
29.2.5 SCI Low Power Mode ........................................................................................ 1578
29.3 LIN......................................................................................................................... 1579
29.3.1 LIN Communication Formats ................................................................................ 1579
29.3.2 LIN Interrupts .................................................................................................. 1596
29.3.3 LIN DMA Interface ............................................................................................ 1596
29.3.4 LIN Configurations ............................................................................................ 1597
29.4 Low-Power Mode........................................................................................................ 1599
29.4.1 Entering Sleep Mode ......................................................................................... 1599
29.4.2 Wakeup......................................................................................................... 1600
29.4.3 Wakeup Timeouts............................................................................................. 1601
29.5 Emulation Mode ......................................................................................................... 1601
29.6 GPIO Functionality ...................................................................................................... 1602
29.6.1 GPIO Functionality ............................................................................................ 1602
29.6.2 Under Reset ................................................................................................... 1602
29.6.3 Out of Reset ................................................................................................... 1603
29.6.4 Open-Drain Feature Enabled on a Pin ..................................................................... 1603
29.6.5 Summary ....................................................................................................... 1603
29.7 SCI/LIN Control Registers.............................................................................................. 1604
29.7.1 SCI Global Control Register 0 (SCIGCR0) ................................................................ 1605
29.7.2 SCI Global Control Register 1 (SCIGCR1) ................................................................ 1606
29.7.3 SCI Global Control Register 2 (SCIGCR2) ................................................................ 1610
29.7.4 SCI Set Interrupt Register (SCISETINT) ................................................................... 1612
29.7.5 SCI Clear Interrupt Register (SCICLEARINT)............................................................. 1615
29.7.6 SCI Set Interrupt Level Register (SCISETINTLVL)....................................................... 1618
29.7.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL)................................................. 1621
29.7.8 SCI Flags Register (SCIFLR)................................................................................ 1624
29.7.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ............................................................ 1631
29.7.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1)........................................................... 1631
29.7.11 SCI Format Control Register (SCIFORMAT) ............................................................ 1632
29.7.12 Baud Rate Selection Register (BRS) ..................................................................... 1633
29.7.13 SCI Data Buffers (SCIED, SCIRD, SCITD) .............................................................. 1635
29.7.14 SCI Pin I/O Control Register 0 (SCIPIO0) ............................................................... 1636
29.7.15 SCI Pin I/O Control Register 1 (SCIPIO1) ............................................................... 1637
29.7.16 SCI Pin I/O Control Register 2 (SCIPIO2) ............................................................... 1638
29.7.17 SCI Pin I/O Control Register 3 (SCIPIO3) ............................................................... 1639
29.7.18 SCI Pin I/O Control Register 4 (SCIPIO4) ............................................................... 1640
23
SPNU563–May 2014 Contents
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