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28.3.2 SPI Global Control Register 1 (SPIGCR1)................................................................. 1479
28.3.3 SPI Interrupt Register (SPIINT0)............................................................................ 1480
28.3.4 SPI Interrupt Level Register (SPILVL)...................................................................... 1482
28.3.5 SPI Flag Register (SPIFLG) ................................................................................. 1483
28.3.6 SPI Pin Control Register 0 (SPIPC0)....................................................................... 1486
28.3.7 SPI Pin Control Register 1 (SPIPC1)....................................................................... 1487
28.3.8 SPI Pin Control Register 2 (SPIPC2)....................................................................... 1489
28.3.9 SPI Pin Control Register 3 (SPIPC3)....................................................................... 1490
28.3.10 SPI Pin Control Register 4 (SPIPC4) ..................................................................... 1491
28.3.11 SPI Pin Control Register 5 (SPIPC5) ..................................................................... 1493
28.3.12 SPI Pin Control Register 6 (SPIPC6) ..................................................................... 1494
28.3.13 SPI Pin Control Register 7 (SPIPC7) ..................................................................... 1496
28.3.14 SPI Pin Control Register 8 (SPIPC8) ..................................................................... 1497
28.3.15 SPI Transmit Data Register 0 (SPIDAT0) ................................................................ 1498
28.3.16 SPI Transmit Data Register 1 (SPIDAT1) ................................................................ 1499
28.3.17 SPI Receive Buffer Register (SPIBUF) ................................................................... 1500
28.3.18 SPI Emulation Register (SPIEMU) ........................................................................ 1502
28.3.19 SPI Delay Register (SPIDELAY) .......................................................................... 1502
28.3.20 SPI Default Chip Select Register (SPIDEF).............................................................. 1505
28.3.21 SPI Data Format Registers (SPIFMT[3:0]) ............................................................... 1506
28.3.22 Interrupt Vector 0 (INTVECT0)............................................................................. 1508
28.3.23 Interrupt Vector 1 (INTVECT1)............................................................................. 1509
28.3.24 Parallel/Modulo Mode Control Register (SPIPMCTRL)................................................. 1510
28.3.25 Multi-buffer Mode Enable Register (MIBSPIE)........................................................... 1513
28.3.26 TG Interrupt Enable Set Register (TGITENST).......................................................... 1514
28.3.27 TG Interrupt Enable Clear Register (TGITENCR)....................................................... 1515
28.3.28 Transfer Group Interrupt Level Set Register (TGITLVST).............................................. 1516
28.3.29 Transfer Group Interrupt Level Clear Register (TGITLVCR)........................................... 1517
28.3.30 Transfer Group Interrupt Flag Register (TGINTFLAG) ................................................. 1518
28.3.31 Tick Count Register (TICKCNT) ........................................................................... 1519
28.3.32 Last TG End Pointer (LTGPEND) ......................................................................... 1520
28.3.33 TGx Control Registers (TGxCTRL)........................................................................ 1521
28.3.34 DMA Channel Control Register (DMAxCTRL) ........................................................... 1524
28.3.35 DMAxCOUNT Register (ICOUNT) ........................................................................ 1526
28.3.36 DMA Large Count (DMACNTLEN) ........................................................................ 1527
28.3.37 Parity/ECC Control Register (PAR_ECC_CTRL)........................................................ 1528
28.3.38 Parity/ECC Status Register (PAR_ECC_STAT)......................................................... 1529
28.3.39 Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1)...... 1530
28.3.40 Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) ...... 1532
28.3.41 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) ................................. 1533
28.3.42 I/O-Loopback Test Control Register (IOLPBKTSTCR) ................................................. 1534
28.3.43 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1).... 1536
28.3.44 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3).... 1538
28.3.45 ECC Diagnostic Control Register (ECCDIAG_CTRL) .................................................. 1539
28.3.46 ECC Diagnostic Status Register (ECCDIAG_STAT) ................................................... 1540
28.3.47 Single Bit Error Address Register - RXRAM (SBERRADDR1) ........................................ 1541
28.3.48 Single Bit Error Address Register - TXRAM (SBERRADDR0) ........................................ 1542
28.4 Multi-buffer RAM ........................................................................................................ 1543
28.4.1 Multi-buffer RAM Auto Initialization ......................................................................... 1544
28.4.2 Multi-buffer RAM Register Summary ....................................................................... 1544
28.4.3 Multi-buffer RAM Transmit Data Register.................................................................. 1545
28.4.4 Multi-buffer RAM Receive Buffer Register ................................................................. 1547
28.5 Parity\ECC Memory..................................................................................................... 1549
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Contents SPNU563–May 2014
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