Datasheet
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27.17.1 CAN Control Register (DCAN CTL) ....................................................................... 1398
27.17.2 Error and Status Register (DCAN ES) .................................................................... 1401
27.17.3 Error Counter Register (DCAN ERRC) ................................................................... 1403
27.17.4 Bit Timing Register (DCAN BTR).......................................................................... 1404
27.17.5 Interrupt Register (DCAN INT) ............................................................................. 1405
27.17.6 Test Register (DCAN TEST) ............................................................................... 1406
27.17.7 Parity Error Code Register (DCAN PERR)............................................................... 1407
27.17.8 ECC Diagnostic Register (DCAN ECCDIAG) ............................................................ 1407
27.17.9 ECC Diagnostic Status Register (DCAN ECCDIAG STAT)............................................ 1408
27.17.10 ECC Control and Status Register (DCAN ECC CS)................................................... 1409
27.17.11 ECC Single Bit Error Code Register (DCAN ECC SERR)............................................ 1410
27.17.12 Auto-Bus-On Time Register (DCAN ABOTR) .......................................................... 1411
27.17.13 Transmission Request X Register (DCAN TXRQ X) .................................................. 1411
27.17.14 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) ............................ 1412
27.17.15 New Data X Register (DCAN NWDAT X)............................................................... 1413
27.17.16 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) ...................................... 1414
27.17.17 Interrupt Pending X Register (DCAN INTPND X)...................................................... 1415
27.17.18 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78) ............................. 1416
27.17.19 Message Valid X Register (DCAN MSGVAL X)........................................................ 1417
27.17.20 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78) .............................. 1418
27.17.21 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78).......................... 1419
27.17.22 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)..................................... 1420
27.17.23 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) ........................................... 1423
27.17.24 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB)...................................... 1424
27.17.25 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL) .......................... 1426
27.17.26 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB) ........ 1428
27.17.27 IF3 Observation Register (DCAN IF3OBS) ............................................................. 1429
27.17.28 IF3 Mask Register (DCAN IF3MSK)..................................................................... 1431
27.17.29 IF3 Arbitration Register (DCAN IF3ARB) ............................................................... 1432
27.17.30 IF3 Message Control Register (DCAN IF3MCTL) ..................................................... 1433
27.17.31 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB) .......................................... 1434
27.17.32 IF3 Update Enable Registers (DCAN IF3UPD12 to DCAN IF3UPD78) ............................ 1435
27.17.33 CAN TX IO Control Register (DCAN TIOC) ............................................................ 1436
27.17.34 CAN RX IO Control Register (DCAN RIOC)............................................................ 1437
28 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP) . 1439
28.1 Overview.................................................................................................................. 1440
28.1.1 Features ........................................................................................................ 1440
28.1.2 Pin Configurations............................................................................................. 1441
28.1.3 MibSPI /SPI Configurations.................................................................................. 1442
28.2 Basic Operation.......................................................................................................... 1442
28.2.1 SPI Mode....................................................................................................... 1442
28.2.2 MibSPI Mode .................................................................................................. 1444
28.2.3 DMA Requests ................................................................................................ 1445
28.2.4 Interrupts ....................................................................................................... 1447
28.2.5 Physical Interface ............................................................................................. 1449
28.2.6 Advanced Module Configuration Options .................................................................. 1453
28.2.7 General-Purpose I/O.......................................................................................... 1471
28.2.8 Low-Power Mode.............................................................................................. 1471
28.2.9 Safety Features................................................................................................ 1471
28.2.10 Test Features ................................................................................................ 1473
28.2.11 Module Configuration ....................................................................................... 1475
28.3 Control Registers........................................................................................................ 1477
28.3.1 SPI Global Control Register 0 (SPIGCR0)................................................................. 1478
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SPNU563–May 2014 Contents
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