Datasheet

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25.5.14 GIO Data Set Registers (GIODSET[A-B]) ................................................................ 1148
25.5.15 GIO Data Clear Registers (GIODCLR[A-B]) ............................................................. 1149
25.5.16 GIO Open Drain Registers (GIOPDR[A-B]) .............................................................. 1149
25.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]).......................................................... 1150
25.5.18 GIO Pull Select Registers (GIOPSL[A-B])................................................................ 1150
25.6 I/O Control Summary ................................................................................................... 1151
26 FlexRay Module .............................................................................................................. 1152
26.1 Overview.................................................................................................................. 1153
26.1.1 Feature List .................................................................................................... 1153
26.1.2 FlexRay Module Block Diagram............................................................................. 1153
26.1.3 FlexRay Module Blocks ...................................................................................... 1156
26.2 Module Operation ....................................................................................................... 1157
26.2.1 Transfer Unit ................................................................................................... 1157
26.2.2 Communication Cycle ........................................................................................ 1168
26.2.3 Communication Modes ....................................................................................... 1169
26.2.4 Clock Synchronization ........................................................................................ 1170
26.2.5 Error Handling ................................................................................................. 1171
26.2.6 Communication Controller States ........................................................................... 1173
26.2.7 Network Management ........................................................................................ 1185
26.2.8 Filtering and Masking......................................................................................... 1185
26.2.9 Transmit Process.............................................................................................. 1188
26.2.10 Receive Process............................................................................................. 1190
26.2.11 FIFO Function................................................................................................ 1191
26.2.12 Message Handling........................................................................................... 1192
26.2.13 Module RAMs ................................................................................................ 1200
26.2.14 Interrupts...................................................................................................... 1211
26.2.15 Minimum Peripheral Clock Frequency .................................................................... 1216
26.2.16 Assignment of FlexRay Configuration Parameters...................................................... 1217
26.2.17 Emulation/Debug Support .................................................................................. 1218
26.3 FlexRay Module Registers ............................................................................................. 1219
26.3.1 Transfer Unit Registers....................................................................................... 1219
26.3.2 Communication Controller Registers ....................................................................... 1267
27 Controller Area Network (DCAN) Module............................................................................ 1359
27.1 Overview.................................................................................................................. 1360
27.1.1 Features ........................................................................................................ 1360
27.1.2 Functional Description ........................................................................................ 1360
27.2 CAN Blocks .............................................................................................................. 1361
27.2.1 CAN Core ...................................................................................................... 1361
27.2.2 Message RAM ................................................................................................. 1361
27.2.3 Message Handler ............................................................................................. 1361
27.2.4 Message RAM Interface...................................................................................... 1362
27.2.5 Register and Message Object Access ..................................................................... 1362
27.2.6 Dual Clock Source ............................................................................................ 1362
27.3 CAN Bit Timing .......................................................................................................... 1363
27.3.1 Bit Time and Bit Rate ......................................................................................... 1363
27.3.2 DCAN Bit Timing Registers .................................................................................. 1365
27.4 CAN Module Configuration............................................................................................. 1367
27.4.1 DCAN RAM Initialization Through Hardware .............................................................. 1367
27.4.2 CAN Module Initialization .................................................................................... 1367
27.5 Message RAM ........................................................................................................... 1370
27.5.1 Structure of Message Objects ............................................................................... 1370
27.5.2 Addressing Message Objects in RAM...................................................................... 1372
27.5.3 Message RAM Representation in Debug/Suspend Mode ............................................... 1373
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SPNU563–May 2014 Contents
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