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24.4.12 Interrupt Offset Register 0 (HTU INTOFF0).............................................................. 1101
24.4.13 Interrupt Offset Register 1 (HTU INTOFF1).............................................................. 1102
24.4.14 Buffer Initialization Mode Register (HTU BIM) ........................................................... 1103
24.4.15 Request Lost Flag Register (HTU RLOSTFL) ........................................................... 1105
24.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL) ..................................................... 1105
24.4.17 BER Interrupt Flag Register (HTU BERINTFL).......................................................... 1106
24.4.18 Memory Protection 1 Start Address Register (HTU MP1S)............................................ 1107
24.4.19 Memory Protection 1 End Address Register (HTU MP1E)............................................. 1107
24.4.20 Debug Control Register (HTU DCTRL) ................................................................... 1108
24.4.21 Watch Point Register (HTU WPR) ........................................................................ 1109
24.4.22 Watch Mask Register (HTU WMR)........................................................................ 1109
24.4.23 Module Identification Register (HTU ID).................................................................. 1110
24.4.24 Parity Control Register (HTU PCR) ....................................................................... 1111
24.4.25 Parity Address Register (HTU PAR) ...................................................................... 1112
24.4.26 Memory Protection Control and Status Register (HTU MPCS)........................................ 1113
24.4.27 Memory Protection Start Address Register 0 (HTU MP0S)............................................ 1116
24.4.28 Memory Protection End Address Register (HTU MP0E) ............................................... 1116
24.5 Double Control Packet Configuration Memory ...................................................................... 1117
24.5.1 Initial Full Address A Register (HTU IFADDRA) .......................................................... 1118
24.5.2 Initial Full Address B Register (HTU IFADDRB) .......................................................... 1118
24.5.3 Initial NHET Address and Control Register (HTU IHADDRCT) ......................................... 1119
24.5.4 Initial Transfer Count Register (HTU ITCOUNT).......................................................... 1120
24.5.5 Current Full Address A Register (HTU CFADDRA) ...................................................... 1121
24.5.6 Current Full Address B Register (HTU CFADDRB) ...................................................... 1122
24.5.7 Current Frame Count Register (HTU CFCOUNT) ........................................................ 1123
24.6 Examples ................................................................................................................. 1124
24.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP ..................... 1124
24.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B ........................ 1124
24.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt................................... 1125
25 General-Purpose Input/Output (GIO) Module ...................................................................... 1126
25.1 Overview.................................................................................................................. 1127
25.2 Quick Start Guide ....................................................................................................... 1128
25.3 Functional Description of GIO Module................................................................................ 1130
25.3.1 I/O Functions................................................................................................... 1130
25.3.2 Interrupt Function ............................................................................................. 1130
25.3.3 GIO Block Diagram ........................................................................................... 1131
25.4 Device Modes of Operation............................................................................................ 1132
25.4.1 Emulation Mode ............................................................................................... 1132
25.4.2 Power-Down Mode (Low-Power Mode) .................................................................... 1132
25.5 GIO Control Registers .................................................................................................. 1133
25.5.1 GIO Global Control Register (GIOGCR0).................................................................. 1134
25.5.2 GIO Interrupt Detect Register (GIOINTDET) .............................................................. 1135
25.5.3 GIO Interrupt Polarity Register (GIOPOL) ................................................................. 1136
25.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) ..................................... 1137
25.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)....................................... 1139
25.5.6 GIO Interrupt Flag Register (GIOFLG) ..................................................................... 1142
25.5.7 GIO Offset Register 1 (GIOOFF1) .......................................................................... 1143
25.5.8 GIO Offset B Register (GIOOFF2).......................................................................... 1144
25.5.9 GIO Emulation A Register (GIOEMU1) .................................................................... 1145
25.5.10 GIO Emulation B Register (GIOEMU2) ................................................................... 1146
25.5.11 GIO Data Direction Registers (GIODIR[A-B])............................................................ 1147
25.5.12 GIO Data Input Registers (GIODIN[A-B])................................................................. 1147
25.5.13 GIO Data Output Registers (GIODOUT[A-B]) ........................................................... 1148
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Contents SPNU563–May 2014
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