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22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ........................ 921
22.3.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) ........................ 922
22.3.54 ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) ............................. 923
22.3.55 ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK)............................ 925
22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) .................... 926
22.3.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR).................. 926
22.3.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG).................................. 927
22.3.59 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)................................ 927
22.3.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)............................. 928
22.3.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) ................................... 928
22.3.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) ................................... 929
22.3.63 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) ............................. 929
22.3.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR).................................... 930
22.3.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR).................................... 930
22.3.66 ADC Parity Control Register (ADPARCR) ................................................................. 931
22.3.67 ADC Parity Error Address Register (ADPARADDR) ..................................................... 932
22.3.68 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) ....................................... 932
22.3.69 ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) ...... 933
22.3.70 ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) ............ 933
22.3.71 ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) ............ 934
22.3.72 ADC Event Group Current Count Register (ADEVCURRCOUNT) ..................................... 935
22.3.73 ADC Event Group Maximum Count Register (ADEVMAXCOUNT) .................................... 935
22.3.74 ADC Group1 Current Count Register (ADG1CURRCOUNT) ........................................... 936
22.3.75 ADC Group1 Maximum Count Register (ADG1MAXCOUNT) .......................................... 936
22.3.76 ADC Group2 Current Count Register (ADG2CURRCOUNT) ........................................... 937
22.3.77 ADC Group2 Maximum Count Register (ADG2MAXCOUNT) .......................................... 937
23 High-End Timer (N2HET) Module ........................................................................................ 938
23.1 Features.................................................................................................................... 939
23.1.1 Overview ......................................................................................................... 939
23.1.2 Block Diagram................................................................................................... 942
23.2 N2HET Functional Description.......................................................................................... 944
23.2.1 Specialized Timer Micromachine ............................................................................. 944
23.2.2 N2HET RAM Organization .................................................................................... 948
23.2.3 Time Base ....................................................................................................... 951
23.2.4 Host Interface ................................................................................................... 953
23.2.5 I/O Control ....................................................................................................... 954
23.2.6 Suppression Filters ............................................................................................. 969
23.2.7 Interrupts and Exceptions ..................................................................................... 969
23.2.8 Hardware Priority Scheme:.................................................................................... 970
23.2.9 N2HET Requests to DMA and HTU.......................................................................... 972
23.3 Angle Functions........................................................................................................... 973
23.3.1 Software Angle Generator..................................................................................... 973
23.4 N2HET Control Registers................................................................................................ 977
23.4.1 Global Configuration Register (HETGCR)................................................................... 978
23.4.2 Prescale Factor Register (HETPFR) ......................................................................... 979
23.4.3 N2HET Current Address Register (HETADDR) ............................................................ 980
23.4.4 Offset Index Priority Level 1 Register (HETOFF1) ......................................................... 980
23.4.5 Offset Index Priority Level 2 Register (HETOFF2) ......................................................... 981
23.4.6 Interrupt Enable Set Register (HETINTENAS).............................................................. 982
23.4.7 Interrupt Enable Clear Register (HETINTENAC) ........................................................... 982
23.4.8 Exception Control Register 1 (HETEXC1)................................................................... 983
23.4.9 Exception Control Register 2 (HETEXC2)................................................................... 984
23.4.10 Interrupt Priority Register (HETPRY) ....................................................................... 985
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Contents SPNU563–May 2014
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