Datasheet

www.ti.com
22.2.8 ADEVT Pin General Purpose I/O Functionality............................................................. 864
22.3 ADC Registers ............................................................................................................ 866
22.3.1 ADC Reset Control Register (ADRSTCR) .................................................................. 868
22.3.2 ADC Operating Mode Control Register (ADOPMODECR) ............................................... 868
22.3.3 ADC Clock Control Register (ADCLOCKCR) .............................................................. 870
22.3.4 ADC Calibration Mode Control Register (ADCALCR) ..................................................... 870
22.3.5 ADC Event Group Operating Mode Control Register (ADEVMODECR) ................................ 872
22.3.6 ADC Group1 Operating Mode Control Register (ADG1MODECR) ...................................... 875
22.3.7 ADC Group2 Operating Mode Control Register (ADG2MODECR) ...................................... 878
22.3.8 ADC Event Group Trigger Source Select Register (ADEVSRC) ......................................... 881
22.3.9 ADC Group1 Trigger Source Select Register (ADG1SRC) ............................................... 882
22.3.10 ADC Group2 Trigger Source Select Register (ADG2SRC).............................................. 883
22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA) ......................................... 884
22.3.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)....................................... 885
22.3.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)....................................... 886
22.3.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG).............................................. 887
22.3.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG).................................................... 888
22.3.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG).................................................... 889
22.3.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) ......................... 890
22.3.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) ............................... 890
22.3.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) ............................... 891
22.3.20 ADC Event Group DMA Control Register (ADEVDMACR) .............................................. 892
22.3.21 ADC Group1 DMA Control Register (ADG1DMACR) .................................................... 894
22.3.22 ADC Group2 DMA Control Register (ADG2DMACR) .................................................... 896
22.3.23 ADC Results Memory Configuration Register (ADBNDCR) ............................................. 898
22.3.24 ADC Results Memory Size Configuration Register (ADBNDEND) ..................................... 899
22.3.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)............................. 900
22.3.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP) ................................... 900
22.3.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP) ................................... 901
22.3.28 ADC Event Group Status Register (ADEVSR) ............................................................ 902
22.3.29 ADC Group1 Status Register (ADG1SR) .................................................................. 903
22.3.30 ADC Group2 Status Register (ADG2SR) .................................................................. 904
22.3.31 ADC Event Group Channel Select Register (ADEVSEL)................................................ 905
22.3.32 ADC Group1 Channel Select Register (ADG1SEL) ...................................................... 906
22.3.33 ADC Group2 Channel Select Register (ADG2SEL) ...................................................... 907
22.3.34 ADC Calibration and Error Offset Correction Register (ADCALR)...................................... 908
22.3.35 ADC State Machine Status Register (ADSMSTATE) .................................................... 908
22.3.36 ADC Channel Last Conversion Value Register (ADLASTCONV) ...................................... 909
22.3.37 ADC Event Group Results' FIFO Register (ADEVBUFFER) ............................................ 910
22.3.38 ADC Group1 Results FIFO Register (ADG1BUFFER)................................................... 911
22.3.39 ADC Group2 Results FIFO Register (ADG2BUFFER)................................................... 912
22.3.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER).......................... 913
22.3.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) ................................ 914
22.3.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) ................................ 915
22.3.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR) .............................................. 916
22.3.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT) ........................................ 917
22.3.45 ADC ADEVT Pin Input Value Register (ADEVTIN)....................................................... 917
22.3.46 ADC ADEVT Pin Set Register (ADEVTSET) .............................................................. 918
22.3.47 ADC ADEVT Pin Clear Register (ADEVTCLR) ........................................................... 918
22.3.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) .......................................... 919
22.3.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) ......................................... 919
22.3.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) .......................................... 920
22.3.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) .................. 920
15
SPNU563–May 2014 Contents
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated