Datasheet
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19.4.2 VIM Input Channel Management ............................................................................. 660
19.5 Interrupt Vector Table (VIM RAM)...................................................................................... 661
19.5.1 Interrupt Vector Table Operation ............................................................................. 661
19.5.2 VIM ECC Syndrome............................................................................................ 662
19.5.3 Interrupt Vector Table Initialization ........................................................................... 663
19.5.4 Interrupt Vector Table ECC Testing.......................................................................... 663
19.6 VIM Wakeup Interrupt.................................................................................................... 665
19.7 Capture Event Sources .................................................................................................. 666
19.8 Examples .................................................................................................................. 666
19.8.1 Examples - Configure CPU To Receive Interrupts......................................................... 666
19.8.2 Examples - Register Vector Interrupt and Index Interrupt Handling ..................................... 667
19.9 VIM Control Registers.................................................................................................... 669
19.9.1 Interrupt Vector Table ECC Status Register (ECCSTAT) ................................................ 670
19.9.2 Interrupt Vector Table ECC Control Register (ECCCTL).................................................. 671
19.9.3 Uncorrectable Error Address Register (UERRADDR) ..................................................... 672
19.9.4 Fallback Vector Address Register (FBVECADDR)......................................................... 672
19.9.5 Single Bit Error Address Register (SBERRADDR)......................................................... 673
19.9.6 VIM Offset Vector Registers................................................................................... 673
19.9.7 IRQ Index Offset Vector Register (IRQINDEX)............................................................. 674
19.9.8 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................ 674
19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3]) ....................................................... 675
19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3]) ............................................. 676
19.9.11 Interrupt Enable Set Registers (REQENASET[0:3])...................................................... 677
19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3]) ................................................... 678
19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])................................................... 679
19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3]) ................................................ 680
19.9.15 IRQ Interrupt Vector Register (IRQVECREG)............................................................. 681
19.9.16 FIQ Interrupt Vector Register (FIQVECREG) ............................................................. 681
19.9.17 Capture Event Register (CAPEVT) ......................................................................... 682
19.9.18 VIM Interrupt Control Registers (CHANCTRL[0:31]) ..................................................... 683
20 Direct Memory Access Controller (DMA) Module .................................................................. 685
20.1 Overview ................................................................................................................... 686
20.1.1 Main Features................................................................................................... 686
20.1.2 System Resources Mapping .................................................................................. 687
20.2 Module Operation......................................................................................................... 688
20.2.1 Memory Space .................................................................................................. 689
20.2.2 DMA Data Access .............................................................................................. 689
20.2.3 Addressing Modes.............................................................................................. 690
20.2.4 DMA Channel Control Packets ............................................................................... 690
20.2.5 Priority Queue................................................................................................... 694
20.2.6 Data Packing and Unpacking ................................................................................. 696
20.2.7 DMA Request ................................................................................................... 699
20.2.8 Auto-Initiation.................................................................................................... 699
20.2.9 Interrupts......................................................................................................... 700
20.2.10 Debugging...................................................................................................... 702
20.2.11 Power Management .......................................................................................... 702
20.2.12 FIFO Buffer..................................................................................................... 703
20.2.13 Channel Chaining ............................................................................................. 704
20.2.14 Request Polarity............................................................................................... 704
20.2.15 Memory Protection ............................................................................................ 705
20.2.16 ECC Checking ................................................................................................. 706
20.2.17 ECC Testing ................................................................................................... 707
20.2.18 Initializing RAM with ECC .................................................................................... 707
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SPNU563–May 2014 Contents
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