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18.2.10 Interrupt......................................................................................................... 623
18.2.11 Power Down Mode............................................................................................ 626
18.2.12 Emulation....................................................................................................... 626
18.2.13 Peripheral Bus Interface...................................................................................... 627
18.3 Example.................................................................................................................... 627
18.3.1 Example: Auto Mode Using Time Based Event Triggering ............................................... 627
18.3.2 Example: Auto Mode Without Using Time Based Triggering ............................................. 628
18.3.3 Example: Semi-CPU Mode.................................................................................... 629
18.3.4 Example: Full-CPU Mode...................................................................................... 629
18.4 CRC Control Registers................................................................................................... 630
18.4.1 CRC Global Control Register 0 (CRC_CTRL0)............................................................. 631
18.4.2 CRC Global Control Register (CRC_CTRL1) ............................................................... 631
18.4.3 CRC Global Control Register 2 (CRC_CTRL2)............................................................. 632
18.4.4 CRC Interrupt Enable Set Register (CRC_INTS) .......................................................... 633
18.4.5 CRC Interrupt Enable Reset Register (CRC_INTR) ....................................................... 635
18.4.6 CRC Interrupt Status Register (CRC_STATUS)............................................................ 637
18.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG).......................................................... 639
18.4.8 CRC Busy Register (CRC_BUSY) ........................................................................... 640
18.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) ..................................... 640
18.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) .................................... 641
18.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1) ............................................... 641
18.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)........................ 642
18.4.13 CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1).................. 642
18.4.14 Channel 1 PSA Signature Low Register (PSA_SIGREGL1) ............................................ 643
18.4.15 Channel 1 PSA Signature High Register (PSA_SIGREGH1) ........................................... 643
18.4.16 Channel 1 CRC Value Low Register (CRC_REGL1)..................................................... 643
18.4.17 Channel 1 CRC Value High Register (CRC_REGH1).................................................... 644
18.4.18 Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1) .............................. 644
18.4.19 Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1) ............................. 644
18.4.20 Channel 1 Raw Data Low Register (RAW_DATAREGL1)............................................... 645
18.4.21 Channel 1 Raw Data High Register (RAW_DATAREGH1).............................................. 645
18.4.22 CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) ................................... 645
18.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) .................................... 646
18.4.24 CRC Current Sector Register 2 (CRC_CURSEC_REG2) ............................................... 646
18.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)........................ 647
18.4.26 CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2).................. 647
18.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2) ............................................ 648
18.4.28 Channel 2 PSA Signature High Register (PSA_SIGREGH2) ........................................... 648
18.4.29 Channel 2 CRC Value Low Register (CRC_REGL2)..................................................... 648
18.4.30 Channel 2 CRC Value High Register (CRC_REGH2).................................................... 649
18.4.31 Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2) .............................. 649
18.4.32 Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2) ............................. 649
18.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2)............................................... 650
18.4.34 Channel 2 Raw Data High Register (RAW_DATAREGH2).............................................. 650
19 Vectored Interrupt Manager (VIM) Module............................................................................ 651
19.1 Overview ................................................................................................................... 652
19.2 Dual VIM for Safety....................................................................................................... 653
19.3 Device Level Interrupt Management ................................................................................... 654
19.3.1 Interrupt Generation at the Peripheral ....................................................................... 654
19.3.2 Interrupt Handling at the CPU................................................................................. 655
19.3.3 Software Interrupt Handling Options ......................................................................... 656
19.4 Interrupt Handling Inside VIM ........................................................................................... 657
19.4.1 VIM Interrupt Channel Mapping............................................................................... 658
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Contents SPNU563–May 2014
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