Datasheet

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16 Error Signaling Module (ESM) ............................................................................................ 547
16.1 Overview ................................................................................................................... 548
16.1.1 Feature List...................................................................................................... 548
16.1.2 Block Diagram................................................................................................... 548
16.2 Module Operation......................................................................................................... 550
16.2.1 Reset Behavior.................................................................................................. 550
16.2.2 ERROR Pin Timing............................................................................................. 551
16.2.3 Forcing an Error Condition .................................................................................... 552
16.3 Recommended Programming Procedure.............................................................................. 553
16.4 ESM Control Registers................................................................................................... 554
16.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)............................... 555
16.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1).............................. 555
16.4.3 ESM Interrupt Enable Set/Status Register 1 (ESMIESR1)................................................ 556
16.4.4 ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) ............................................. 556
16.4.5 ESM Interrupt Level Set/Status Register 1 (ESMILSR1).................................................. 557
16.4.6 ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) ............................................... 557
16.4.7 ESM Status Register 1 (ESMSR1) ........................................................................... 558
16.4.8 ESM Status Register 2 (ESMSR2) ........................................................................... 558
16.4.9 ESM Status Register 3 (ESMSR3) ........................................................................... 559
16.4.10 ESM ERROR Pin Status Register (ESMEPSR) .......................................................... 559
16.4.11 ESM Interrupt Offset High Register (ESMIOFFHR) ...................................................... 560
16.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR) ....................................................... 561
16.4.13 ESM Low-Time Counter Register (ESMLTCR) ........................................................... 562
16.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)................................................ 562
16.4.15 ESM Error Key Register (ESMEKR)........................................................................ 563
16.4.16 ESM Status Shadow Register 2 (ESMSSR2) ............................................................. 563
16.4.17 ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) ..................................... 564
16.4.18 ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) .................................. 564
16.4.19 ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) ............................................. 565
16.4.20 ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4) ........................................... 565
16.4.21 ESM Interrupt Level Set/Status Register 4 (ESMILSR4) ................................................ 566
16.4.22 ESM Interrupt Level Clear/Status Register 4 (ESMILCR4) ............................................. 566
16.4.23 ESM Status Register 4 (ESMSR4) ......................................................................... 567
16.4.24 ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) ..................................... 568
16.4.25 ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) .................................. 568
16.4.26 ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) ............................................. 569
16.4.27 ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) ........................................... 569
16.4.28 ESM Interrupt Level Set/Status Register 7 (ESMILSR7) ................................................ 570
16.4.29 ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) ............................................. 570
16.4.30 ESM Status Register 7 (ESMSR7) ......................................................................... 571
17 Real-Time Interrupt (RTI) Module ........................................................................................ 572
17.1 Overview ................................................................................................................... 573
17.1.1 Features.......................................................................................................... 573
17.1.2 Industry Standard Compliance Statement................................................................... 573
17.2 Module Operation......................................................................................................... 574
17.2.1 Counter Operation .............................................................................................. 574
17.2.2 Interrupt/DMA Requests ....................................................................................... 576
17.2.3 RTI Clocking..................................................................................................... 577
17.2.4 Synchronizing Timer Events to Network Time (NTU)...................................................... 577
17.2.5 Digital Watchdog (DWD)....................................................................................... 580
17.2.6 Low Power Modes.............................................................................................. 583
17.2.7 Halting Debug Mode Behaviour............................................................................... 583
17.3 Control Registers ......................................................................................................... 584
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Contents SPNU563–May 2014
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